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SAF-C161PI Datasheet(PDF) 73 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 73 Page - Infineon Technologies AG |
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73 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-25 1999-08 The Context Pointer CP This non-bit addressable register is used to select the current register context. This means that the CP register value determines the address of the first General Purpose Register (GPR) within the current register bank of up to 16 wordwide and/or bytewide GPRs. Note: It is the user’s responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location. If this condition is not met, unexpected results may occur. • Do not set CP below the IRAM start address, i.e. 00’FA00 H/00’F600H/00’F200H (referring to an IRAM size of 1/2/3 KByte) • Do not set CP above 00’FDFE H • Be careful using the upper GPRs with CP above 00’FDE0 H The CP register can be updated via any instruction which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register. The Switch Context instruction (SCXT) allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle. CP Context Pointer SFR (FE10 H/08H) Reset value: FC00 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 11 cp 0 r r r r rw r Bit Function cp Modifiable portion of register CP Specifies the (word) base address of the current register bank. When writing a value to register CP with bits CP.11...CP.9 = ‘000’, bits CP.11...CP.10 are set to ‘11’ by hardware, in all other cases all bits of bit field “cp” receive the written value. |
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