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SAF-C161PI Datasheet(PDF) 49 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 49 Page - Infineon Technologies AG |
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49 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-1 1999-08 4 The Central Processing Unit (CPU) Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated results. As the CPU is the main engine of the C161PI controller, it is also affected by certain actions of the peripheral subsystem. Since a four stage pipeline is implemented in the C161PI, up to four instructions can be processed in parallel. Most instructions of the C161PI are executed in one machine cycle (2 CPU clock periods) due to this parallelism. This chapter describes how the pipeline works for sequential and branch instructions in general, and which hardware provisions have been made to speed the execution of jump instructions in particular. The general instruction timing is described including standard and exceptional timing. While internal memory accesses are normally performed by the CPU itself, external peripheral or memory accesses are performed by a particular on-chip External Bus Controller (EBC), which is automatically invoked by the CPU whenever a code or data address refers to the external address space. Figure 4-1 CPU Block Diagram |
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