 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SAF-C161PI Datasheet(PDF) 89 Page - Infineon Technologies AG |
|
|
|||||||||||||||||||||||||||||
SAF-C161PI Datasheet(HTML) 89 Page - Infineon Technologies AG |
|
|
89 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-7 1999-08 Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests. The priority increases with the numerical value of ILVL, so 0000 B is the lowest and 1111B is the highest priority level. When more than one interrupt request on a specific level gets active at the same time, the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced. Again the group priority increases with the numerical value of GLVL, so 00 B is the lowest and 11B is the highest group priority. Note: All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities. Otherwise an incorrect interrupt vector will be generated. Upon entry into the interrupt service routine, the priority level of the source that won the arbitration and who’s priority level is higher than the current CPU level, is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack. The interrupt system of the C161PI allows nesting of up to 15 interrupt service routines of different priority levels (level 0 cannot be arbitrated). Interrupt requests that are programmed to priority levels 15 or 14 (ie, ILVL=111X B) will be serviced by the PEC, unless the COUNT field of the associated PECC register contains zero. In this case the request will instead be serviced by normal interrupt processing. Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing. Note: Priority level 0000 B is the default level of the CPU. Therefore a request on level 0 will never be serviced, because it can never interrupt the CPU. However, an enabled interrupt request on level 0000 B will terminate the C161PI’s Idle mode and reactivate the CPU. For interrupt requests which are to be serviced by the PEC, the associated PEC channel number is derived from the respective ILVL (LSB) and GLVL (see figure below). So programming a source to priority level 15 (ILVL=1111 B) selects the PEC channel group 7...4, programming a source to priority level 14 (ILVL=1110 B) selects the PEC channel group 3...0. The actual PEC channel number is then determined by the group priority field GLVL. Simultaneous requests for PEC channels are prioritized according to the PEC channel number, where channel 0 has lowest and channel 8 has highest priority. Note: All sources that request PEC service must be programmed to different PEC channels. Otherwise an incorrect PEC channel may be activated. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
