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TMS320F28375DPZP Datasheet(PDF) 182 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 182 Page - Texas Instruments |
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182 / 226 page ![]() 9.3.3 EMIF Chip Select Memory Map The EMIF1 memory map is the same for both CPU subsystems. EMIF2 is available only on the CPU1 subsystem. The EMIF memory map is shown in Table 9-4. Table 9-4. EMIF Chip Select Memory Map EMIF CHIP SELECT SIZE(2) START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS EMIF1_CS0n - Data 256M × 16 0x8000 0000 0x8FFF FFFF Yes EMIF1_CS2n - Program + Data(3) 2M × 16 0x0010 0000 0x002F FFFF Yes EMIF1_CS3n - Program + Data 512K × 16 0x0030 0000 0x0037 FFFF Yes EMIF1_CS4n - Program + Data 393K × 16 0x0038 0000 0x003D FFFF Yes EMIF2_CS0n - Data(1) 3M × 16 0x9000 0000 0x91FF FFFF EMIF2_CS2n - Program + Data(1) 4K × 16 0x0000 2000 0x0000 2FFF Yes (Data only) (1) Available only on the CPU1 subsystem. (2) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory sizes because of pin mux setting. See Section 7.4.1 to find the available address lines for your use case. (3) The 2M × 16 size is for a 32-bit interface with the assumption that 16-bit accesses are not performed; hence, byte enables are not used (tied to active value on board). If byte enables are used, then the maximum size is smaller because byte enables are muxed with address pins (see Section 7.4.1) . If 16-bit memory is used, then the maximum size is 1M × 16. 9.3.4 Peripheral Registers Memory Map The peripheral registers memory map can be found in Table 9-5. The peripheral registers can be assigned to either the CPU1 or CPU2 subsystems except where noted in Table 9-5. Registers in the peripheral frames share a secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the TMS320F2837xD Dual-Core Microcontrollers Technical Reference Manual for details on the CPU subsystem and secondary master selection. Table 9-5. Peripheral Registers Memory Map REGISTERS STRUCTURE NAME START ADDRESS END ADDRESS PROTECTED (1) CLA ACCESS DMA ACCESS AdcaResultRegs ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes AdcbResultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes AdccResultRegs ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes CpuTimer0Regs (2) CPUTIMER_REGS 0x0000 0C00 0x0000 0C07 CpuTimer1Regs (2) CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F CpuTimer2Regs (2) CPUTIMER_REGS 0x0000 0C10 0x0000 0C17 PieCtrlRegs (2) (5) PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF Cla1SoftIntRegs (5) CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF Yes – CLA only, no CPU access DmaRegs (2) DMA_REGS 0x0000 1000 0x0000 11FF Cla1Regs (2) CLA_REGS 0x0000 1400 0x0000 147F Peripheral Frame 1 EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes EPwm2Regs EPWM_REGS 0x0000 4100 0x0000 41FF Yes Yes Yes EPwm3Regs EPWM_REGS 0x0000 4200 0x0000 42FF Yes Yes Yes EPwm4Regs EPWM_REGS 0x0000 4300 0x0000 43FF Yes Yes Yes EPwm5Regs EPWM_REGS 0x0000 4400 0x0000 44FF Yes Yes Yes EPwm6Regs EPWM_REGS 0x0000 4500 0x0000 45FF Yes Yes Yes EPwm7Regs EPWM_REGS 0x0000 4600 0x0000 46FF Yes Yes Yes EPwm8Regs EPWM_REGS 0x0000 4700 0x0000 47FF Yes Yes Yes EPwm9Regs EPWM_REGS 0x0000 4800 0x0000 48FF Yes Yes Yes EPwm10Regs EPWM_REGS 0x0000 4900 0x0000 49FF Yes Yes Yes TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 182 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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