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TMS320F28375DPZP Datasheet(PDF) 184 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 184 Page - Texas Instruments |
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184 / 226 page  Table 9-5. Peripheral Registers Memory Map (continued) REGISTERS STRUCTURE NAME START ADDRESS END ADDRESS PROTECTED (1) CLA ACCESS DMA ACCESS EPwmXbarRegs (3) EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes OutputXbarRegs (3) OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes GpioCtrlRegs (3) GPIO_CTRL_REGS 0x0000 7C00 0x0000 7D7F Yes GpioDataRegs (2) GPIO_DATA_REGS 0x0000 7F00 0x0000 7F2F Yes Yes UsbaRegs (3) USB_REGS 0x0004 0000 0x0004 0FFF Yes Emif1Regs EMIF_REGS 0x0004 7000 0x0004 77FF Yes Emif2Regs (3) EMIF_REGS 0x0004 7800 0x0004 7FFF Yes CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes IpcRegs (2) IPC_REGS_CPU1 IPC_REGS_CPU2 0x0005 0000 0x0005 0023 Yes FlashPumpSemaphoreRegs (2) FLASH_PUMP_SEMAPHORE_REGS 0x0005 0024 0x0005 0025 Yes DevCfgRegs (3) DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes AnalogSubsysRegs (3) ANALOG_SUBSYS_REGS 0x0005 D180 0x0005 D1FF Yes ClkCfgRegs (4) CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes CpuSysRegs (2) CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes RomPrefetchRegs (3) ROM_PREFETCH_REGS 0x0005 E608 0x0005 E60B Yes DcsmZ1Regs (2) DCSM_Z1_REGS 0x0005 F000 0x0005 F02F Yes DcsmZ2Regs (2) DCSM_Z2_REGS 0x0005 F040 0x0005 F05F Yes DcsmCommonRegs (2) DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes MemCfgRegs (2) MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes Emif1ConfigRegs (2) EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Yes Emif2ConfigRegs (3) EMIF2_CONFIG_REGS 0x0005 F4A0 0x0005 F4BF Yes AccessProtectionRegs (2) ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes MemoryErrorRegs (2) MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes RomWaitStateRegs (3) ROM_WAIT_STATE_REGS 0x0005 F540 0x0005 F541 Yes Flash0CtrlRegs (2) FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes Flash0EccRegs (2) FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes (1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated. (2) A unique copy of these registers exist on each CPU subsystem. (3) These registers are available only on the CPU1 subsystem. (4) These registers are mapped to either CPU1 or CPU2 based on a semaphore. (5) The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register sets. TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 184 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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