TMS320F28375DPZP datasheet(186/226 Pages) TI

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9.3.5.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs).

Each shared RAM block can be owned by either CPU subsystem based on the configuration of respective bits in

the GSxMSEL register.

All GSx RAM blocks have parity.

When a GSx RAM block is owned by a CPU subsystem, the CPUx and CPUx.DMA will have full access to that

RAM block whereas the other CPUy and CPUy.DMA will only have read access (no fetch/write access).

Table 9-8 shows the master access for the GSx RAM.

Table 9-8. Master Access for GSx RAM

(With Assumption That all Other Access Protections are Disabled)

GSxMSEL

CPU

INSTRUCTION

FETCH

READ

WRITE

CPUx.DMA READ

CPUx.DMA

WRITE

CPU1

Yes

CPU2

–

Yes

–

Yes

–

CPU1

–

Yes

–

Yes

–

CPU2

Yes

The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).

9.3.5.4 CPU Message RAM (CPU MSGRAM)

These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for

interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA read/write

access from its own CPU subsystem, and CPU/DMA read only access from the other subsystem.

This RAM has parity.

9.3.5.5 CLA Message RAM (CLA MSGRAM)

These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access

to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU

and CLA both have read access to both MSGRAMs.

This RAM has parity.

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

www.ti.com

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TMS320F28375DPZP Datasheet(PDF) 186 Page - Texas Instruments

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