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TMS320F28375DPZP Datasheet(PDF) 188 Page - Texas Instruments

Part # TMS320F28375DPZP
Description  TMS320F2837xD Dual-Core Microcontrollers
PDF  226 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F28375DPZP Datasheet(HTML) 188 Page - Texas Instruments

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9.5 Bus Architecture – Peripheral Connectivity
Table 9-10 shows a broad view of the peripheral and configuration register accessibility from each bus master.
Peripherals can be individually assigned to the CPU1 or CPU2 subsystem (for example, ePWM can be assigned
to CPU1 and eQEP assigned to CPU2). Peripherals within peripheral frames 1 or 2 will all be mapped to the
respective secondary master as a group (if SPI is assigned to CPUx.DMA, then McBSP is also assigned to
CPUx.DMA).
Table 9-10. Bus Master Peripheral Access
PERIPHERALS
(BY BUS ACCESS TYPE)
CPU1.DMA
CPU1.CLA1
CPU1
CPU2
CPU2.CLA1
CPU2.DMA
Peripherals that can be assigned to CPU1 or CPU2 and have common selectable Secondary Masters
Peripheral Frame 1:
•
ePWM
•
SDFM
•
eCAP(1)
•
eQEP(1)
•
CMPSS(1)
•
DAC(1)
Y
Y
Y
Y
Y
Y
Peripheral Frame 1:
•
HRPWM
Y
Y
Y
Peripheral Frame 2:
•
SPI
•
McBSP
Y
Y
Y
Y
Y
Y
Peripheral Frame 2:
•
uPP Configuration(1)
Y
Y
Y
Peripherals that can be assigned to CPU1 or CPU2 subsystems
SCI
Y
Y
I2C
Y
Y
CAN
Y
Y
ADC Configuration
Y
Y
Y
Y
EMIF1
Y
Y
Y
Y
Peripherals and Device Configuration Registers only on CPU1 subsystem
EMIF2
Y
Y
USB
Y
Device Capability, Peripheral Reset, Peripheral CPU
Select
Y
GPIO Pin Mapping and Configuration
Y
Analog System Control
Y
uPP Message RAMs
Y
Y
Reset Configuration
Y
Accessible by only one CPU at a time with Semaphore
Clock and PLL Configuration
Y
Y
Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master (2)
System Configuration
(WD, NMIWD, LPM, Peripheral Clock Gating)
Y
Y
Flash Configuration(3)
Y
Y
CPU Timers
Y
Y
DMA and CLA Trigger Source Select
Y
Y
GPIO Data(4)
Y
Y
Y
Y
ADC Results
Y
Y
Y
Y
Y
Y
(1)
These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2)
Each CPUx and CPUx.CLA1 can only access its own copy of these registers.
(3)
At any given time, only one CPU can perform program or erase operations on the Flash.
TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D
TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021
www.ti.com
188
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D
TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D



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