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MCP48CMB21 Datasheet(PDF) 41 Page - Microchip Technology |
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MCP48CMB21 Datasheet(HTML) 41 Page - Microchip Technology |
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41 / 106 page ![]() 2019 Microchip Technology Inc. DS20006160A-page 41 MCP48CXBXX 3.1 Positive Power Supply Input (VDD) VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS. The power supply at the VDD pin should be as clean as possible for good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground as close as possible to the pin. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate noise present in application boards. 3.2 Ground (VSS) The VSS pin is the device ground reference. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application PCB (Printed Circuit Board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.3 Voltage Reference Pin (VREF) The VREF pin is either an input or an output. When the DAC’s voltage reference is configured as the VREF pin, the pin is an input. When the DAC’s voltage reference is configured as the internal band gap, the pin is an output. When the DAC’s voltage reference is configured as the VREF pin, there are two options for this voltage input: VREF pin voltage is buffered or unbuffered. The buffered option is offered in cases where the external reference voltage does not have sufficient current capability to not drop its voltage when connected to the internal resistor ladder circuit. When the DAC’s voltage reference is configured as the device VDD, the VREF pin is disconnected from the internal circuit. When the DAC’s voltage reference is configured as the internal band gap, the VREF pin’s drive capability is minimal, so the output signal should be buffered. See Section 5.2 “Voltage Reference Selection” and Register 4-2 for more details on the configuration bits. 3.4 No Connect (NC) The NC pin is not internally connected to the device. 3.5 Analog Output Voltage Pins (VOUT0, VOUT1) VOUT0 and VOUT1 are the DAC analog voltage output pins. Each DAC output has an output amplifier. The DAC output range depends on the selection of the voltage reference source (and potential Output Gain selection). These are: • Device VDD - The full-scale range of the DAC output is from VSS to approximately VDD. •VREF pin - The full-scale range of the DAC output is from VSS to G x VRL, where G is the gain selection option (1X or 2X). • Internal Band Gap - The full-scale range of the DAC output is from VSS to G X VBG, where G is the gain selection option (1X or 2X). In Normal mode, the DC impedance of the output pin is about 1 . In Power-Down mode, the output pin is internally connected to a known pull-down resistor of 1k , 100 k, or open. The Power-Down selection bits settings are shown in Register 4-3 (Table 5-5). 3.6 Latch/High-Voltage Command Pin (LAT/HVC) The DAC output value update event can be controlled and synchronized using the LAT pin, for one or both channels, on a single or different devices. The LAT pin controls the effect of the volatile wiper registers, VRxB:VRxA, PDxB:PDxA and Gx bits on the DAC output. If the LAT pin is held at VIH, the values sent to the volatile wiper registers and configuration bits have no effect on the DAC outputs. Once voltage on the pin transitions to VIL, the values in the volatile wiper registers and configuration bits are transferred to the DAC outputs. The pin is level-sensitive, so writing to the volatile wiper registers and configuration bits, while it is being held at VIL, will trigger an immediate change in the outputs. For dual output devices in MSOP and DFN packages, the LAT pin controls both channels at the same time. The HVC pin allows the device’s MTP memory to be programmed for the MCP48CMBXX devices. The programming voltage supply should provide 7.5V and at least 6.4 mA. Note: The HVC pin should have voltages greater than 5.5V present only during the MTP programming operation. Using voltages greater than 5.5V for an extended time on the pin may cause device reliability issues. |
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