MCP48CMB21 datasheet(57/106 Pages) MICROCHIP

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DS20006160A-page 57

MCP48CXBXX

5.2

Voltage Reference Selection

The resistor ladder has up to four sources for the

reference voltage. The selection of the voltage

reference source is specified with the volatile

VREF1:VREF0 configuration bits (see Register 4-2).

The selected voltage source is connected to the VRL

node (see Figure 5-3 and Figure 5-4).

FIGURE 5-3:

Resistor Ladder Reference

Voltage Selection Block Diagram.

The four voltage source options for the Resistor Ladder

are:

VDD pin voltage

Internal band gap voltage reference (VBG)

VREF pin voltage - unbuffered

VREF pin voltage - internally buffered

On a POR/BOR event, the default configuration state or

the value written in the nonvolatile register is latched into

the volatile VREF1:VREF0 configuration bits.

If the VREF pin is used with an external voltage source,

then the user must select between Buffered or

Unbuffered mode.

5.2.1

USING VDD AS VREF

When the user selects the VDD as reference, the VREF

pin voltage is not connected to the Resistor Ladder.

The VDD voltage is internally connected to the Resistor

Ladder.

5.2.2

USING AN EXTERNAL VREF

SOURCE IN UNBUFFERED MODE

In this case, the VREF pin voltage may vary from VSS to

VDD. The voltage source should have a low-output

impedance. If the voltage source has a high-output

impedance, then the voltage on the VREF pin could be

lower than expected. The resistor ladder has a typical

impedance of 71 k

 and a typical capacitance of 29 pF.

If a single VREF pin is supplying multiple DACs, the

VREF pin source must have adequate current capability

to support the number of DACs. It must be assumed

that the resistor ladder resistance (RRL) of each DAC is

at the minimum specified resistance and these resis-

tances are in parallel.

If the VREF pin is tied to the VDD voltage, selecting

the VDD Reference mode (VREF1:VREF0 = ‘00’) is

recommended.

5.2.3

USING AN EXTERNAL VREF

SOURCE IN BUFFERED MODE

The VREF pin voltage may be from 0V to VDD. The input

buffer (amplifier) provides low offset voltage, low noise,

and a very high input impedance, with only minor

limitations on the input range and frequency response.

Any variation or noises on the reference source can

directly affect the DAC output. The reference voltage

needs to be as clean as possible for accurate DAC

performance.

FIGURE 5-4:

Reference Voltage Selection

Implementation Block Diagram.

VRL

VDD

Buffer

VREF1:VREF0

VREF

Band Gap

Note 1: The Band Gap voltage (VBG) is 1.214V

typical. The band gap output goes

through the buffer with a 2X gain to

create the VRL voltage. See Table 5-1

for additional information on the band

gap circuit.

VDD

VRL

Band Gap(1)

(1.214V typical)

VDD

PD1:PD0 and

VREF1:VREF0

PD1:PD0 and

VREF1:VREF0

VDD

PD1:PD0 and

VREF1:VREF0

VREF

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