MCP48CMB21 datasheet(58/106 Pages) MICROCHIP

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MCP48CXBXX

DS20006160A-page 58

 2019 Microchip Technology Inc.

5.2.4

USING THE INTERNAL BAND GAP

AS VOLTAGE REFERENCE

The Internal Band Gap is designed to drive the Resistor

Ladder Buffer.

If the Internal Band Gap is selected, then the band gap

voltage source will drive the external VREF pins. The

VREF1 pin must be left unloaded in this mode. The

voltage reference source can be independently

selected on devices with two DAC channels, but

restrictions apply:

•The VDD mode can be used without issues on any

channel.

• When the Internal Band Gap is selected as the

voltage source, all the VREF pins are connected to

its output. The use of the Unbuffered mode is only

possible on VREF0, because it’s the only one that

can be loaded.

• When using the Internal Band Gap mode on

channel 0, channel 1 must be put in Buffered

External VREF mode or VDD Reference mode and

the VREF1 pin must be left unloaded.

The resistance of the resistor ladder (RRL) is targeted

to be 71 k

 (10%), which means a minimum

resistance of 63.9 k

.

The band gap selection can be used across the VDD

voltages while maximizing the VOUT voltage ranges.

For VDD voltages below the Gain  VBG voltage, the

output for the upper codes will be clipped to the VDD

voltage. Table 5-4 shows the maximum DAC register

code given device VDD and Gain bit setting.

5.3

Output Buffer/VOUT Operation

The Output Driver buffers the wiper voltage (VW) of the

Resistor Ladder.

The DAC output is buffered with a low-power, precision

output amplifier with selectable gain. This amplifier

provides a rail-to-rail output with low offset voltage and low

noise. The amplifier’s output can drive the resistive and

high-capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications. Refer

to Section 1.0 “Electrical Characteristics” for the

specifications of the output amplifier.

Figure 5-5 shows a block diagram of the output driver

circuit.

FIGURE 5-5:

Output Driver Block Diagram.

Power-Down logic also controls the output buffer

operation (see Section 5.5 “Power-Down Operation”

for additional information on Power-Down). In any of

the three Power-Down modes, the output amplifier is

powered down and its output becomes a high

impedance to the VOUT pin.

5.3.1

PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (see Register 4-4) and the VRL

reference selection (see Register 4-2).

The Gain options are:

a) Gain of 1, with either the VDD or VREF pin used

as reference voltage.

b) Gain of 2, only when the VREF pin or the Internal

Band Gap is used as reference voltage. The

VREF pin voltage should be limited to VDD/2.

When the reference voltage selection (VRL) is

the device’s VDD voltage, the G bit is ignored

and a gain of 1 is used.

Table 5-2 shows the gain bit operation.

TABLE 5-1:

VOUT USING BAND GAP

Max DAC Code(1)

Comment

12-bit 10-bit 8-bit

5.5

FFFh

3FFh

FFh VOUT(max) =1.214V(3)

FFFh

3FFh

FFh VOUT(max) =2.428V(3)

2.7

FFFh

3FFh

FFh VOUT(max) =1.214V

(3)

FFFh

3FFh

FFh VOUT(max) =2.428V

1.8

FFFh

3FFh

FFh VOUT(max) =1.214V

2(2) BBCh2EFhBBh 1.8V

Note 1:

Without the VOUT pin voltage being clipped.

Recommended to use the Gain = 1 setting.

When VBG = 1.214V typical.

Note:

The load resistance must be kept higher

than 2 k

 to maintain stability of the

analog output and have it meet electrical

specifications.

Gain

(1x or 2x)

VOUT

PD1:PD0

VDD

PD1:PD0

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