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MCP48CMB21 Datasheet(PDF) 49 Page - Microchip Technology |
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MCP48CMB21 Datasheet(HTML) 49 Page - Microchip Technology |
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49 / 106 page ![]() 2019 Microchip Technology Inc. DS20006160A-page 49 MCP48CXBXX Register 4-2 shows the format of the Voltage Reference Control register. Each DAC has two bits to control the source of the voltage reference of the DAC. This register is for the volatile memory locations. The width of this register is 2 times the number of DACs for the device. REGISTER 4-2: VOLTAGE REFERENCE (VREF) CONTROL REGISTERS (08h/18h) (VOLATILE/NONVOLATILE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-n R/W-n R/W-n R/W-n Single —— ——— —— ——— —— —(1) —(1) VR0B VR0A Dual — — — — — — — — — — — — VR1B VR1A VR0B VR0A bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown = Single-channel device = Dual-channel device Single Dual bit 15-2 bit 15-4 Unimplemented: Read as ‘0’ bit 1-0 bit 3-0 VRxB-VRxA: DAC Voltage Reference Control bits 11 = VREF pin (Buffered); VREF buffer enabled 10 = VREF pin (Unbuffered); VREF buffer disabled 01 = Internal Band Gap(2) (1.214V typical); VREF buffer enabled. VREF voltage driven when powered-down. 00 = VDD (Unbuffered); VREF buffer disabled. Use this state with power-down bits for lowest current. Note 1: Unimplemented bit, read as ‘0’. 2: When the Internal Band Gap is selected, the band gap voltage source will continue to output the voltage on the VREF pin in any of the Power-Down modes. To reduce the power consumption to its lowest level (Band Gap disabled), after selecting the desired Power-Down mode, the voltage reference should be changed to VDD or VREF pin unbuffered (“00” or ‘10’), which turns off the Internal Band Gap circuitry. After wake-up, the user needs to reselect the Internal Band Gap (“01”) for the voltage reference source. |
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