MCP48CMB21 datasheet(47/106 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006160A-page 47

MCP48CXBXX

TABLE 4-2:

FACTORY DEFAULT POR/BOR VALUES (MTP MEMORY UNPROGRAMMED)

Function

POR/BOR Value

Function

POR/BOR Value

00h Volatile DAC0 Register

7Fh

1FFh

7FFh

10h Nonvolatile DAC0 Wiper

7Fh

1FFh

7FFh

01h Volatile DAC1 Register

7Fh

1FFh

7FFh

11h Nonvolatile DAC1 Wiper

7Fh

1FFh

7FFh

02h Reserved

—

12h Reserved

—

03h Reserved

—

13h Reserved

—

04h Reserved

—

14h Reserved

—

05h Reserved

—

15h Reserved

—

06h Reserved

—

16h Reserved

—

07h Reserved

—

17h Reserved

—

08h Volatile VREF Register

0000h 0000h 0000h

18h Nonvolatile VREF

0000h

09h Volatile Power-Down

0000h 0000h 0000h

19h Nonvolatile Power-Down

0000h

0Ah Volatile Gain and Status

0080h 0080h 0080h

1Ah NV Gain (1)

0000h

0Bh Reserved

0000h 0000h 0000h

1Bh NV WiperLock™

Technology Register(1)

0000h

0Ch General Purpose MTP(1)

—

1Ch General Purpose MTP(1)

0000h

0Dh General Purpose MTP(1)

0000h 0000h 0000h

1Dh General Purpose MTP(1)

0000h

0Eh General Purpose MTP(1)

0000h 0000h 0000h

1Eh General Purpose MTP(1)

0000h

0Fh General Purpose MTP(1)

0000h 0000h 0000h

1Fh General Purpose MTP(1)

0000h

Legend:

Volatile Memory address range

Nonvolatile Memory address range

Not implemented

Note 1:

On nonvolatile devices only (MCP48CMBXX).

The “1” bit is the POR status bit, which is set after the POR event and cleared after address 0Ah is read.

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