MCP48CMB21 datasheet(97/106 Pages) MICROCHIP

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DS20006160A-page 97

MCP48CXBXX

APPENDIX B: TERMINOLOGY

B.1

Resolution

The resolution is the number of DAC output states that

divide the full-scale range. For the 12-bit DAC, the

resolution is 212, meaning the DAC code ranges from

0 to 4095.

B.2

Least Significant Bit (LSb)

This is the voltage difference between two successive

codes. For a given output voltage range, it is divided by

the resolution of the device (Equation B-1). The range

may be VDD (or VREF) to VSS (ideal), the DAC register

codes across the linear range of the output driver

(Measured 1), or full-scale to zero-scale (Measured 2).

EQUATION B-1:

LSb VOLTAGE

CALCULATION

B.3

Monotonic Operation

The monotonic operation means that the device’s

output voltage (VOUT) increases with every 1 code step

(LSb) increment (from VSS to the DAC’s reference

voltage (VDD or VREF)).

FIGURE B-1:

VW (VOUT).

B.4

Full-Scale Error (EFS)

The Full-Scale Error (see Figure B-3) is the error on

the VOUT pin relative to the expected VOUT voltage

(theoretical) for the maximum device DAC register

code (code FFFh for 12-bit, code 3FFh for 10-bit, and

code FFh for 8-bit) (see Equation B-2). The error is

dependent on the resistive load on the VOUT pin (and

where that load is tied to, such as VSS or VDD). For

loads (to VSS) greater than specified, the full-scale

error will be greater.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

EQUATION B-2:

FULL-SCALE ERROR

Note:

When there are 2N resistors in the resistor

ladder and 2N tap points, the full-scale

DAC register code is the resistor element

(1 LSb) from the source reference voltage

(VDD or VREF).

2N = 4096 (MCP48CXB2X)

= 1024 (MCP48CXB1X)

= 256 (MCP48CXB0X)

Ideal:

Measured 1 (12-bit device):

VLSb IDEAL



VDD

----------- or

VREF

-------------

VLSb Measured



VOUT(@4032) VOUT(@64)

–

4032 64

–



---------------------------------------------------------------

VLSb

VOUT(@FS) VOUT(@ZS)

–

-----------------------------------------------------------

Measured 2:

40h

3Fh

3Eh

03h

02h

01h

00h

Voltage (VW ~= VOUT)

VW (@ tap)

VS0

VS1

VS3

VS63

VS64

VW =

VSn + VZS(@ Tap 0)

n = 0

n = ?

Where:

EFS is expressed in LSb

VOUT(@FS) is the VOUT voltage when the DAC

VIDEAL(@FS) is the ideal output voltage when the

DAC register code is at full-scale.

VLSb(IDEAL) is the theoretical voltage step size.

EFS

VOUT(@FS) VIDEAL(@FS)

–

VLSb IDEAL



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