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MCP48CMB21 Datasheet(PDF) 44 Page - Microchip Technology |
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MCP48CMB21 Datasheet(HTML) 44 Page - Microchip Technology |
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44 / 106 page  MCP48CXBXX DS20006160A-page 44 2019 Microchip Technology Inc. When the rising VDD voltage crosses the VPOR trip point, the following occurs: • The default DAC POR value is latched into the volatile DAC register. • The default DAC POR Configuration bit values are latched into the volatile configuration bits. • POR Status bit is set (‘1’). • The Reset Delay Timer (tPORD) starts; when the reset delay timer (tPORD) times out, the SPI serial interface is operational. During this delay time, the SPI interface will not accept commands. • The Device Memory Address pointer is forced to 00h. The analog output (VOUT) state is determined by the state of the volatile configuration bits and the DAC register. This is called a Power-on Reset (event). Figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. FIGURE 4-1: Power-on Reset Operation. Below min. operating voltage VPOR TPORD2OD VDD(MIN) BOR reset, volatile DAC register = 000h volatile VRxB:VRxA = 00 VRAM volatile Gx = 0 volatile PDxB:PDxA = 11 VBOR POR starts Reset Delay Timer. When timer times out, the SPI interface can operate (if VDD VDD(MIN)) Default Device configuration latched into volatile configuration bits and DAC register. POR status bit is set (‘1’) Device in unknown state Device in POR state POR reset forced active Normal Operation Device in Power-D own state Device in unknown state Volatile memory retains data value Volatile memory becomes corrupted VDD(MIN) TPORD2OD Below min. operating voltage Device in unknown state Normal Operation Device in Power-D own state Device in unknown state Volatile memory retains data value POR Event Device in known state Volatile memory becomes corrupted VBOR VPOR VRAM Case 1: VDD Ramp Case 2: VDD Step |
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