MCP48CMB21 datasheet(65/106 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006160A-page 65

MCP48CXBXX

6.0

SPI SERIAL INTERFACE

MODULE

The MCP48CXBXX’s SPI Serial Interface Module is a

4-wire interface. The devices operate only as slaves

(do not generate the master clock). Figure 6-1 shows a

typical SPI interface connection.

FIGURE 6-1:

Typical SPI Interface.

The frame content (commands) for the MCP48CXBXX

are defined in Section 7.0 “Device Commands”.

6.1

Overview

This

section

discusses

some

the

specific

characteristics of the MCP48CXBXX’s SPI Serial

Interface Module. This is to assist in the development of

your application.

The following sections discuss some of these

device-specific characteristics:

• Communication Data Rates

• POR/BOR

• Interface Pins (CS, SCK, SDI, SDO, and

LAT/HVC)

• Device Memory Address

• SPI Modes

The MCP48CXBXX devices support the SPI serial

protocol. This SPI operates in Slave mode (does not

generate the serial clock).

The SPI interface uses four pins. These are:

•CS - Chip Select

• SCK - Serial Clock

• SDI - Serial Data In

• SDO - Serial Data Out

A fifth pin is used if a write is being done in the MTP

memory. This pin is HVC - High Voltage Command

(customer manufacturing only, multiplexed with LAT0

functionality).

The HVC pin is used to program the MTP memory.

This is intended to be used only during the customer’s

factory production flow. On volatile devices, the HVC

pin is high-voltage tolerant. To enter a high voltage

command, the HVC pin must be greater than the VIHH

voltage.

Typical SPI Interfaces are shown in Figure 6-1. In the

SPI interface, the Master’s Output pin is connected to

the Slave’s Input pin, and the Master’s Input pin is

connected to the Slave’s Output pin.

The MCP48CXBXX SPI module supports two (of the

four) standard SPI modes. These are Mode

0,0 and

1,1. The SPI mode is determined by the state of the

SCK pin (VIH or VIL) when the CS pin transitions from

inactive (VIH) to active (VIL).

6.2

Communication Data Rates

The MCP48CXBXX supports clock rates (bit rates) of

up to 25 MHz for read, and 50 MHz for Write

commands.

For most applications, the write time will be considered

more important, since that is how the device operation

is controlled.

6.3

POR/BOR

On a POR/BOR event, the SPI Serial Interface Module

state machine is reset, which includes forcing the

device’s Memory Address pointer to 00h.

6.4

Interface Pins (CS, SCK, SDI, SDO,

and LAT/HVC)

The operation of the four interface pins and the

High-Voltage command (HVC) pin is discussed in this

section. The serial interface works on 24-bit

boundaries. The CS pin frames the SPI commands.

6.4.1

SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal in the

device. The value on this pin is latched on the rising

edge of the SCK signal.

6.4.2

SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

Once the CS pin is forced to the active level (VIL), the

SDO pin is driven. The state of the SDO pin is deter-

mined by the serial bit’s position in the command, the

selected command, and if there is a state of command

error (CMDERR).

6.4.3

SERIAL CLOCK (SCK)

(SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 50 MHz

for Write commands and 25 MHz for read commands.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

MCP48CXBXX

Host

Controller

Typical SPI Interface Connections

Other Devices

(Master)

(Slave)

SDI

SDO

SDI

GPIO

SCK

LAT/HVC

GPIO

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