MCP48CMB21 datasheet(70/106 Pages) MICROCHIP

70 / 106 page

MCP48CXBXX

DS20006160A-page 70

 2019 Microchip Technology Inc.

7.1

Command Byte

The Command Byte has three fields, the Address (5

bits), the Command (2 bits), and 1 Reserved bit, see

Figure 7-1.

The device memory is accessed when the master

sends a proper Command Byte to select the desired

operation. The memory location getting accessed is

contained in the Command Byte’s AD4:AD0 bits. The

action desired is contained in the Command Byte’s

C1:C0 bits, see Figure 7-5. C1:C0 determines if the

desired memory location will be read or written.

As the Command Byte is loaded into the device (on

the SDI pin), the device’s SDO pin drives. The SDO

pin will output high bits for the first seven bits of that

command. On the 8th bit, the SDO pin will output the

CMDERR bit state.

7.2

Data Bytes

The Read and Write commands use Data Bytes, see

Figure 7-1. The D16 bit is currently unused, and

corresponds to the position on the SDO data of the

CMDERR bit.

7.3

Error Condition

The CMDERR bit indicates if the five address bits

received (AD4:AD0) and the two command bits

received (C1:C0) are a valid combination. The

CMDERR bit is high if the combination is valid and low

if the combination is invalid.

The command error bit will also be low if a write to a

nonvolatile address has been specified and another

SPI command occurs before the CS pin is driven

inactive (VIH).

SPI commands that do not have a multiple of 24

clocks are ignored.

Once an error condition has occurred, any following

commands are ignored. All following SDO bits will be

low until the CMDERR condition is cleared by forcing

the CS pin to the Inactive state (VIH) or doing a POR.

7.3.1

ABORTING A TRANSMISSION

All SPI transmissions must have the correct number of

SCK pulses to be executed. The command is not

executed until the complete number of clocks have

been received. Some commands also require the CS

pin to be forced inactive (VIH). If the CS pin is forced to

the Inactive state (VIH), the serial interface is reset.

Partial commands are not executed.

SPI is more susceptible to noise than other bus

protocols. The most likely case is that this noise

corrupts the value of the data being clocked into the

MCP48CXBXX or the SCK pin is injected with extra

clock pulses. This may cause data to be corrupted in

the device, or a command error to occur, since the

address and command bits were not a valid combina-

tion. The extra SCK pulse will also cause the SPI data

(SDI) and clock (SCK) to be out of sync. Forcing the

CS pin to the Inactive state (VIH) resets the serial inter-

face. The SPI interface will ignore activity on the SDI

and SCK pins until the CS pin transition to the active

state is detected (VIH to VIL).

7.4

Continuous Commands

The device supports the ability to execute commands

continuously. While the CS pin is in Active state (VIL),

any sequence of valid commands may be received.

The following example is a valid sequence of events:

CS pin driven active (VIL)

Read command

Write command (Volatile memory)

Write command (Nonvolatile memory)

CS pin driven inactive (VIH)

7.5

Write Command

The Write command is a 24-bit command. The Write

command can be issued to both the volatile and non-

volatile memory locations. The format of the command

is shown in Figure 7-2.

A Write command to a volatile memory location

changes that location after a properly formatted Write

command (24-clock) has been received.

A Write command to a nonvolatile memory location will

only start a write cycle after a properly formatted Write

command (24-clock) has been received and the CS

pin transitions to the Inactive state (VIH).

Note 1: When the MCP48CXBXX does not

receive data, it is recommended that the

CS pin be forced to the inactive level (VIL).

Note 1: While the CS pin is active, only one type of

command should be issued. When

changing commands, it is recommended

to take the CS pin inactive then force it

back to the active state.

2: Long command strings should be broken

down into shorter command strings. This

reduces the probability of noise on the

SCK pin corrupting the desired SPI

command string.

Note: Writes to volatile memory locations depend

on the state of the WiperLock™ Technology

bits.

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