MCP48CMB21 datasheet(66/106 Pages) MICROCHIP

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MCP48CXBXX

DS20006160A-page 66

 2019 Microchip Technology Inc.

TABLE 6-1:

SCK FREQUENCY

6.4.4

THE CS SIGNAL

The CS signal is used to select the device and frame a

command sequence. To start a command, or

sequence of commands, the CS signal must transition

from the inactive state (VIH) to an active state (VIL).

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

If an error condition occurs for an SPI command, then

the Command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (VIL). To exit the

error condition, the user must take the CS pin to the

VIH level.

When the CS pin returns to the inactive state (VIH), the

SPI module resets (including the address pointer).

While the CS pin is in the inactive state (VIH), the serial

interface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,

SDO, and SCK signals.

6.4.5

THE HVC SIGNAL

The high voltage requirement of the HVC pin for

programming MTP registers ensure that a device in

normal operation does not corrupt the values.

6.5

Device Memory Address

The memory address is the 5-bit value that specifies

the location in the device’s memory that the specified

command will operate on.

On a POR/BOR event, the device’s Memory Address

pointer is forced to 00h.

6.6

SPI Modes

The SPI module supports two (of the four) standard

SPI modes. These are Mode 0,0 and 1,1. The

MCP48CXBXX’s

SPI

mode

automatically

determined based on the Master’s configured mode.

Memory Type Access

Command

Read

Write

Nonvolatile

Memory

SDI, SDO

25 MHz

50 MHz (1)

Volatile

Memory

SDI, SDO

25 MHz

50 MHz (1)

Note 1: After issuing a Write command to the NV

locations, the internal write cycle must be

completed before the next SPI command

addressing the NV locations is received

(twc).

Note: There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

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