MCP48CMB21 datasheet(100/106 Pages) MICROCHIP

100 / 106 page

MCP48CXBXX

DS20006160A-page 100

 2019 Microchip Technology Inc.

B.12

Differential Nonlinearity (DNL)

The

Differential

Nonlinearity (DNL)

Error

(see

Figure B-5) is the measure of step size between codes

in actual transfer function. The ideal step size between

codes is 1 LSb. A DNL Error of zero would imply that

every code is exactly 1 LSb wide. If the DNL Error is

less than 1 LSb, the DAC guarantees monotonic output

and no missing codes. Equation B-7 shows how to cal-

culate the DNL Error between any two adjacent codes

in LSb.

EQUATION B-7:

DNL ERROR

FIGURE B-5:

DNL ACCURACY.

B.13

Settling Time

The Settling time is the time delay required for the VOUT

voltage to settle into its new output value. This time is

measured from the start of code transition to when the

VOUT voltage is within the specified accuracy.

For the MCP48CXBXX, the settling time is a measure

of the time delay until the VOUT voltage reaches within

0.5 LSb of its final value, when the volatile DAC register

changes from 1/4 to 3/4 of the FSR (12-bit device: 400h

to C00h).

B.14

Major-Code Transition Glitch

Major-Code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes the state. It is normally

specified as the area of the glitch in nV-Sec and is

measured when the digital code is changed by 1 LSb at

the major carry transition (Example: 011...111 to

100... 000, or 100... 000 to 011 ... 111).

B.15

Digital Feed-Through

The digital feed-through is the glitch that appears at the

analog output caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec and is measured with a full-scale change

(Example: all 0s to all 1s and vice versa) on the digital

input pins. The digital feed-through is measured when

the DAC is not being written to the output register.

B.16

-3 dB Bandwidth

This is the frequency of the signal at the VREF pin that

causes the voltage at the VOUT pin to fall to -3 dB from

a static value on the VREF pin. The output decreases

due to the RC characteristics of the resistor ladder and

the characteristics of the output buffer.

B.17

Power-Supply Sensitivity (PSS)

PSS indicates how the output of the DAC is affected by

changes in the supply voltage. PSS is the ratio of the

change in VOUT to a change in VDD for mid-scale output

of the DAC. The VOUT is measured while the VDD is

varied from 5.5V to 2.7V as a step (VREF voltage held

constant) and expressed in %/%, which is the %

change of the DAC output voltage with respect to the %

change of the VDD voltage.

EQUATION B-8:

PSS CALCULATION

Where:

DNL is expressed in LSb.

VOUT(Code = n) = The measured DAC output

voltage with a given DAC

VLSb(Measured) = For Measured:

(VOUT(4032) - VOUT(64))/3968

EDNL

VOUT(code = n+1) VOUT(code = n)

–



VLSb Measured



------------------------------------------------------------------------------------1

–

010

001

000

Analog

Output

(LSb)

DAC Input Code

011

111

100 101

DNL = 2 LSb

DNL = 0.5 LSb

110

Ideal Transfer Function

Actual Transfer Function

Where:

PSS is expressed in %/%.

VOUT(@5.5V) = The measured DAC output

voltage with VDD = 5.5V

VOUT(@2.7V) = The measured DAC output

voltage with VDD = 2.7V

PSS

VOUT(@5.5V) VOUT(@2.7V)

–

 V

OUT(@5.5V)



5.5V 2.7V

–

 5.5V





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