CEC1712 datasheet(6/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 6

 2020-2021 Microchip Technology Inc.

1.0

GENERAL DESCRIPTION

The CEC1712 device is a low power integrated embedded controller designed with strong cryptographic support. The

CEC1712 is a highly-configurable, mixed-signal, advanced I/O controller architecture. It contains a 32-bit ARM® Cortex-

M4 processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embed-

ded in the design, is used to store the power on/boot sequence and APIs available during run time. When VTR_CORE

is applied to the device, the secure boot loader API is used to download the custom firmware image from the system’s

shared SPI Flash device, thereby allowing system designers to customize the device’s behavior.

The CEC1712 device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR). The

CEC1712 has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the

CEC1712 to interface with the latest platform controller hubs and will lower the overall power consumed by the device,

Whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation.

The CEC1712 secure boot loader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES-

256, ECDSA P-384, SHA-384 cryptographic hardware accelerators. The CEC1712 hardware accelerators support 128-

bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic

asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the

ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP stor-

age for private keys and IDs. Additional features supported include Key Revocation, Roll back protection and DICE.

CEC1712 offers a software development system interface that includes a Trace FIFO debug port and a 2-pin Serail wire

debug (SWD)/ JTAG interface.

1.1

Family Features

TABLE 1-1:

CEC1712 FEATURE LIST

Features

CEC1712 -84 WFBGA

Package

84 pin WFBGA

Device ID

0023_A2

Boundary Scan JTAG ID

0223_2445

CPU

32-bit ARM® Cortex-M4

SRAM

256 kB

Code/Data Options (Primary use)

224kB/32kB

Battery Backed SRAM

64 bytes

Trace FIFO Debug Port

Yes

Internal DMA Channels

32-bit Timer

16-bit Timer

Capture Timer Registers

ICT Channels

Compare Timer

Yes

Watchdog Timer (WDT)

Hibernation Timer

Week Timer

Sub Week Timer

RTC

RTOS Timer

Keyboard Matrix scan support

SMBus 2.0 Host Controllers

I2C Host Controllers

CEC1712 Datasheet(PDF) 6 Page - Microchip Technology

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