CEC1712 datasheet(74/338 Pages) MICROCHIP

74 / 338 page

CEC1712

DS00003416C-page 74

 2020-2021 Microchip Technology Inc.

The bit definitions for the Sleep Enable, Clock Required and Reset Enable Registers are defined in the Sleep Enable

4.9

Sleep Enable n Registers

4.9.1

SLEEP ENABLE N REGISTER

4.9.2

CLOCK REQUIRED N REGISTER

4.9.3

PERIPHERAL RESET ENABLE N REGISTER

All register addresses are naturally aligned on 32-bit boundaries. Offsets for registers that are smaller than 32 bits are

reserved and must not be used for any other purpose.

Offset

See Sleep Enable Register Assignments Table in Section 3.0, "Device Inventory"

Bits

Description

Type

Default

Reset

Event

31:0

SLEEP_ENABLE

1=Block is commanded to sleep at next available moment

0=Block is free to use clocks as necessary

Unassigned bits are reserved. They must be set to ‘1b’ when writ-

ten. When read, unassigned bits return the last value written.

R/W

RESET

_SYS

Offset

See Sleep Enable Register Assignments Table in Section 3.0, "Device Inventory"

Bits

Description

Type

Default

Reset

Event

31:0

CLOCK_REQUIRED

1=Bock requires clocks

0=Block does not require clocks

Unassigned bits are reserved and always return 0 when read.

R0h

RESET

_SYS

Offset

See Sleep Enable Register Assignments Table in Section 3.0, "Device Inventory"

Bits

Description

Type

Default

Reset

Event

31:0

PERIPHERAL_RESET_ENABLE

1= Will allow issue parallel reset to the peripherals. This is self

clearing bit.

W0h

RESET

_SYS

CEC1712 Datasheet(PDF) 74 Page - Microchip Technology

CEC1712 Datasheet(HTML) 74 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL