CEC1712 datasheet(97/338 Pages) MICROCHIP

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DS00003416C-page 97

CEC1712

7.11.1

CONFIGURATION

The DMA Controller is enabled via the ACTIVATE bit in DMA Main Control Register register.

Each DMA Channel must also be individually enabled via the CHANNEL_ACTIVATE bit in the DMA Channel N Activate

Before starting a DMA transaction on a DMA Channel the host must assign a DMA Master to the channel via HARD-

WARE_FLOW_CONTROL_DEVICE. The host must not configure two different channels to the same DMA Master at

the same time.

Data will be transfered between the DMA Master, starting at the programmed DEVICE_ADDRESS, and the targeted

memory location, starting at the MEMORY_START_ADDRESS. The address for either the DMA Master or the targeted

memory location may remain static or it may increment. To enable the DMA Master to increment its address set the

INCREMENT_DEVICE_ADDRESS bit. To enable the targeted memory location to increment its addresses set the

INCREMENT_MEMORY_ADDRESS. The DMA transfer will continue as long as the target memory address being

accessed is less than the MEMORY_END_ADDRESS. If the DMA Controller detects that the memory location it is

attempting to access on the Target is equal to the MEMORY_END_ADDRESS it will notify the DMA Master that the

transaction is done. Otherwise the Data will be transferred in packets. The size of the packet is determined by the

TRANSFER_SIZE.

7.11.2

OPERATION

The DMA Controller is designed to move data from one memory location to another.

7.11.2.1

Establishing a Connection

A DMA Master will initiate a DMA Transaction by requesting access to a channel. The DMA arbiter, which evaluates

each channel request using a basic round robin algorithm, will grant access to the DMA master. Once granted, the chan-

nel will hold the grant until it decides to release it, by notifying the DMA Controller that it is done.

If Firmware wants to prevent any other channels from being granted while it is active it can set the LOCK_CHANNEL bit.

7.11.2.2

Initiating a Transfer

Once a connection is established the DMA Master will issue a DMA request to start a DMA transfer. If Firmware wants

to have a transfer request serviced it must set the RUN bit to have its transfer requests serviced.

Firmware can initiate a transaction by setting the TRANSFER_GO bit. The DMA transfer will remain active until either

the Master issues a Terminate or the DMA Controller signals that the transfer is DONE. Firmware may terminate a trans-

action by setting the TRANSFER_ABORT bit.

Data may be moved from the DMA Master to the targeted Memory address or from the targeted Memory Address to the

DMA Master. The direction of the transfer is determined by the TRANSFER_DIRECTION bit.

Once a transaction has been initiated firmware can use the STATUS_DONE bit to determine when the transaction is

completed. This status bit is routed to the interrupt interface. In the same register there are additional status bits that

indicate if the transaction completed successfully or with errors. These bits are OR’d together with the STATUS_DONE

bit to generate the interrupt event. Each status be may be individually enabled/disabled from generating this event.

7.11.2.3

Reusing a DMA Channel

After a DMA Channel controller has completed, firmware must clear both the DMA Channel N Control Register and the

DMA Channel N Interrupt Status Register. After both have been cleared to 0, the Channel Control Register can then be

configured for the next transaction.

7.11.2.4

CRC Generation

A CRC generator can be attached to a DMA channel in order to generate a CRC on the data as it is transfered from the

source to the destination. The CRC used is the CRC-32 algorithm used in IEEE 802.3 and many other protocols, using

the polynomial x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1. The CRC generation takes

place in parallel with the data transfer; enabling CRC will not increase the time to complete a DMA transaction. The CRC

generator has the optional ability to automatically transfer the generated CRC to the destination after the data transfer

has completed.

Note:

Before initiating a DMA transaction via firmware the hardware flow control must be disabled via the DIS-

ABLE_HARDWARE_FLOW_CONTROL bit.

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