CEC1712 datasheet(73/338 Pages) MICROCHIP

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DS00003416C-page 73

CEC1712

In HEAVY SLEEP, the 48 MHz PLL is shut down. On wake, the 32 MHz Ring Oscillator is used to provide a clock source

for the 48MHz clock domain until the PLL locks to the 32KHz clock domain. The ring oscillator starts immediately on

wake, so there is no latency for the EC to start after a wake, However, the ring oscillator is only accurate to ±50%, so

any device that requires an accurate 48MHz clock will not operate correctly until the PLL locks.The time to lock latency

for the PLL is shown in Table 4-9, "System Sleep Modes".

The SLEEP_ALL bit is automatically cleared when the processor responds to an interrupt. This applies to non-wake

interrupts as well as wake interrupts, in the event an interrupt occurs between the time the processor issued a WAIT

FOR INTERRUPT instruction and the time the system completely enters the sleep state.

Any JTAG access to the ARM/STAP will cause a pseudo-wake event where the clocks are turned on, but the CHip is

still in sleep (SLEEP_EN's and SLEEP_ALL stay in the same state).This way the access can occur over JTAG, without

changing the parts state, and the part can go back to sleep once the JTAG access is over.

4.7.4.1

Wake-Only Events

Some devices which respond to an external master require the 48MHz clock domain to operate but do not necessarily

require and immediate processing by the EC. Wake-only events provide the means to start the 48MHz clock domain

without triggering an EC interrupt service routine. This events are grouped into a single GIRQ, GIRQ22. Events that are

enabled in that GIRQ will start the clock domain when the event occurs, but will not invoke an EC interrupt. The

SLEEP_ENABLE flags all remain asserted. If the activity for the event does not in turn trigger another EC interrupt, the

CLOCK_REQUIRED for the block will re-assert and the configured sleep state will be re-entered.

4.8

EC Registers

Registers for this block are shown in the following summary table. Addresses for each register are determined by adding

the offset to the Base Address for the Power, Clocks, and Resets Block in the Block Overview and Base Address Table

in Section 3.0, "Device Inventory".

TABLE 4-8:

Offset

Name

System Sleep Control Register

Processor Clock Control Register

Slow Clock Control Register

Oscillator ID Register

10h

PCR Power Reset Status Register

14h

Power Reset Control Register

18h

System Reset Register

1Ch

Reserved

20h

TEST

30h

Sleep Enable 0 Register

34h

Sleep Enable 1 Register

38h

Sleep Enable 2 Register

3Ch

Sleep Enable 3 Register

40h

Sleep Enable 4 Register

50h

Clock Required 0 Register

54h

Clock Required 1 Register

58h

Clock Required 2 Register

5Ch

Clock Required 3 Register

60h

Clock Required 4 Register

70h

Reset Enable 0 Register

74h

Reset Enable 1 Register

78h

Reset Enable 2 Register

7Ch

Reset Enable 3 Register

80h

Reset Enable 4 Register

84h

Peripheral Reset Lock Register

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