CEC1712 datasheet(98/338 Pages) MICROCHIP

98 / 338 page

CEC1712

DS00003416C-page 98

 2020-2021 Microchip Technology Inc.

CRC generation is subject to a number of restrictions:

• The CRC is only generated on channels that have the CRC hardware. See Table 7-10, "Channel Register Sum-

mary" for a definition of which channels have the ability to generate a CRC

• The DMA transfer must be 32-bits

• If CRC is enabled, DMA interrupts are inhibited until the CRC is completed, including the optional post-transfer

copy of it is enabled

• The CRC must be initialized by firmware. The value FFFFFFFFh must be written to the Data Register in order to

initialize the generator for the standard CRC-32-IEEE algorithm

• The CRC will

be bit‐order reversed and inverted as required by the CRC algorithm

7.11.2.5

Block Fill Option

A Fill engine can be attached to a DMA channel in order to provide a fast mechanism to set a block of memory to a fixed

value (for example, clearing a block of memory to zero). The block fill operation runs approximately twice as fast as a

memory-to-memory copy.

In order to fill memory with a constant value, firmware must configure the channel in the following order:

Set the DMA Channel N Fill Data Register to the desired fill value

Set the DMA Channel N Fill Enable Register to ‘1b’, enabling the Fill engine

Set the DMA Channel N Control Register to the following values:

- RUN = 0

- TRANSFER_DIRECTION = 0 (memory destination)

- INCREMENT_MEMORY_ADDRESS = 1 (increment memory address after each transfer)

- INCREMENT_DEVICE_ADDRESS = 1

- DISABLE_HARDWARE_FLOW_CONTROL = 1 (no hardware flow control)

- TRANSFER_SIZE = 1, 2 or 4 (as required)

- TRANSFER_ABORT = 0

- TRANSFER_GO = 1 (this starts the transfer)

7.12

EC Registers

The DMA Controller consists of a Main Block and a number of Channels. Table 7-9, "Main Register Summary" lists the

registers in the Main Block and Table 7-10, "Channel Register Summary" lists the registers in each channel. Addresses

for each register are determined by adding the offset to the Base Address for the DMA Controller Block in the Block

Overview and Base Address Table in Section 3.0, "Device Inventory".

Registers are listed separately for the Main Block of the DMA Controller and for a DMA Channel. Each Channel has the

same set of registers. The absolute register address for registers in each channel are defined by adding the Base

Address for the DMA Controller Block, the Offset for the Channel shown in Table 7-8, "DMA Channel Offsets" to the

offsets listed in Table 7-9, "Main Register Summary" or Table 7-10, "Channel Register Summary".

TABLE 7-8:

DMA CHANNEL OFFSETS

Instance Name

Channel Number

Offset

DMA Controller

Main Block

000h

DMA Controller

040h

DMA Controller

080h

DMA Controller

0C0h

DMA Controller

100h

DMA Controller

140h

DMA Controller

180h

DMA Controller

1C0h

DMA Controller

200h

DMA Controller

240h

DMA Controller

280h

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