CEC1712 datasheet(102/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 102

 2020-2021 Microchip Technology Inc.

7.12.7

DMA CHANNEL N CONTROL REGISTER

Offset

10h

Bits

Description

Type

Default

Reset

Event

31:26 Reserved

RES

25 TRANSFER_ABORT

This is used to abort the current transfer on this DMA Channel. The

aborted transfer will be forced to terminate immediately.

R/W

RESET

24 TRANSFER_GO

This is used for the Firmware Flow Control DMA transfer.

This is used to start a transfer under the Firmware Flow Control.

Do not use this in conjunction with the Hardware Flow Control;

DISABLE_HARDWARE_FLOW_CONTROL must be set in order for

this field to function correctly.

R/W

RESET

23 Reserved

RES

22:20 TRANSFER_SIZE

This is the transfer size in Bytes of each Data Packet transfer.

The transfer size must be a legal transfer size. Valid sizes are 1, 2

and 4 Bytes.

R/W

RESET

19 DISABLE_HARDWARE_FLOW_CONTROL

Setting this bit to ‘1’b will Disable Hardware Flow Control. When

disabled, any DMA Master device attempting to communicate to the

DMA over the DMA Flow Control Interface will be ignored.

This should be set before using the DMA channel in Firmware Flow

Control mode.

R/W

RESET

18 LOCK_CHANNEL

This is used to lock the arbitration of the Channel Arbiter on this

channel once this channel is granted.

Once this is locked, it will remain on the arbiter until it has completed

it transfer (either the Transfer Aborted, Transfer Done or Transfer

Terminated conditions).

Note:

This setting may starve other channels if the locked chan-

nel takes an excessive period of time to complete.

R/W

RESET

17 INCREMENT_DEVICE_ADDRESS

If this bit is ‘1’b, the DEVICE_ADDRESS will be incremented by

TRANSFER_SIZE after every Data Packet transfer

R/W

RESET

16 INCREMENT_MEMORY_ADDRESS

If this bit is ‘1’b, the MEMORY_START_ADDRESS will be incre-

mented by TRANSFER_SIZE after every Data Packet transfer

Note:

If this is not set, the DMA will never terminate the transfer

on its own. It will have to be terminated through the Hard-

ware Flow Control or through a DMA Channel Con-

trol:Transfer Abort.

R/W

RESET

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