CEC1712 datasheet(87/338 Pages) MICROCHIP

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DS00003416C-page 87

CEC1712

5.8

Low Power Modes

The ARM processor can enter Sleep or Deep Sleep modes internally. This action will cause an output signal Clock

Required to be turned off, allowing clocks to be stopped from the chip level. However, Clock Required will still be held

active, or set to active, unless all of the following conditions exist:

• No interrupt is pending.

• An input signal Sleep Enable from the chip level is active.

• The Debug JTAG port is inactive (reset or configured not present).

In addition, regardless of the above conditions, a chip-level input signal Force Halt may halt the processor and remove

Clock Required.

5.9

Description

5.9.1

BUS CONNECTIONS

There are three bus connections used from CEC1712 EC block, which are directly related to the IP bus ports. See

Figure 5-1, "ARM M4 Based Embedded Controller I/O Block Diagram".

For the mapping of addresses at the chip level, see Section 3.0, "Device Inventory".

5.9.1.1

Closely Coupled Instruction Fetch Bus

As shown in Figure 5-1, the AHB-Lite ICode port from the IP is converted to a more conventional SRAM memory-style

bus and connected to the on-chip memory resources with routing priority appropriate to Instruction Fetches.

5.9.1.2

Closely Coupled Data Bus

As shown in Figure 5-1, the AHB-Lite DCode port from the IP is converted to a more conventional SRAM memory-style

bus and connected to the on-chip memory resources with routing priority appropriate to fast Data Read/Write accesses.

5.9.1.3

Chip-Level System Bus

As shown in Figure 5-1, the AHB-Lite System port from the IP is converted from AHB-Lite to fully arbitrated multi-master

capability (the AMBA 2 defined AHB bus: see Reference [5], ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A,

13 May 1999). Using this bus, all addressable on-chip resources are available. The multi-mastering capability supports

the Microchip DMA and EMI features if present, as well as the Bit-Banding feature of the IP itself.

As also shown in Figure 5-1, the Closely-Coupled memory resources are also available through this bus connection

using aliased addresses. This is required in order to allow Bit Banding to be used in these regions, but it also allows

them to be accessed by DMA and other bus masters at the chip level.

5.9.2

INSTRUCTION PIPELINING

There are no special considerations except as defined by ARM documentation.

5.10

Debugger Access Support

An external Debugger accesses the chip through a JTAG standard interface. The ARM Debug Access Port supports

both the 2-pin SWD (Serial Wire Debug) interface and the 4-pin JTAG interface.

As shown in Figure 5-1, "ARM M4 Based Embedded Controller I/O Block Diagram", other resources at the chip level

that share the JTAG port pins; for example chip-level Boundary Scan.

By default, debug access is disabled when the EC begins executing code. EC code enables debugging by writing the

Debug Enable Register in the EC Subsystem Registers block.

Note:

Registers with properties such as Write-1-to-Clear (W1C), Read-to-Clear and FIFOs need to be handled

with appropriate care when being used with the bit band alias addressing scheme. Accessing such a reg-

ister through a bit band alias address will cause the hardware to perform a read-modify-write, and if a W1C-

type bit is set, it will get cleared with such an access. For example, using a bit band access to the Interrupt

Aggregator, including the Interrupt Enables and Block Interrupt Status to clear an IRQ will clear all active

IRQs.

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