CEC1712 datasheet(82/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 82

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•HTM

AHB Trace Macrocell. This is an optional subblock that is not included.

•ITM

Instrumentation Trace Macrocell subblock. Provides a HW Trace interface for “printf”-style reports from instru-

mented firmware builds, with timestamping also provided.

• MEM-AP

A generic term for an AP that connects to a memory-mapped bus on-chip. For this product, this term is synony-

mous with the AHB Access Port, AHB-AP.

•NVIC

Nested Vectored Interrupt Controller subblock. Accepts external interrupt inputs. See References [2], ARM Lim-

ited: ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010 and [4], ARM® Generic Interrupt

Controller Architecture version 1.0 Architecture Specification, IHI0048A, September 2008.

• PPB

Private Peripheral Bus: A specific APB bus with local connectivity within the EC.

•ROM Table

A ROM-based data structure in the Debug section that allows an external Debugger and/or a FW monitor to

determine which of the Debug features are present.

•SWJ-DP

Serial Wire / JTAG Debug Port, the DP option selected by Microchip for the DAP.

•TPA

Trace Port Analyzer: any off-chip device that uses the TPIU output.

•TPIU

Trace Port Interface Unit subblock. Multiplexes and buffers Trace reports from the ETM and ITM subblocks.

•WIC

Wake-Up Interrupt Controller. This is an optional subblock that is not included.

5.3.2

MICROCHIP TERMS AND ACRONYMS

• Interrupt Aggregator

This is a module that may be present at the chip level, which can combine multiple interrupt sources onto single

interrupt inputs at the EC, causing them to share a vector.

•PMU

Processor Memory Unit, this is a module that may be present at the chip level containing any memory resources

that are closely-coupled to the CEC1712 EC. It manages accesses from both the EC processor and chip-level

bus masters.

5.4

ARM M4 IP Interfaces

This section defines only the interfaces to the ARM IP itself. For the interfaces of the entire block, see Section 5.5, "Block

External Interfaces".

The CEC1712 IP has the following major external interfaces, as shown in Figure 5-1, "ARM M4 Based Embedded Con-

troller I/O Block Diagram":

• ICode AHB-Lite Interface

• DCode AHB-Lite Interface

• System AHB-Lite Interface

• Debug (JTAG) Interface

• Trace Port Interface

• Interrupt Interface

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