CEC1712 datasheet(14/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 14

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2.4.9

GATED STATE

This column defines the internal value of an input signal when either its emulated power well is inactive or it is not

selected by the GPIO alternate function MUX. A value of “No Gate” means that the internal signal always follows the

pin even when the emulated power well is inactive.

2.4.10

NOTES

The below notes are for all tables in this chapter.

Note:

VBAT powered signals do not support power emulation and must program the PGS bit field to 00b (VTR)

Note:

Gated state is only meaningful to the operation of input signals. A gated state on an output pin defines the

internal behavior of the GPIO MUX and does not imply pin behavior.

Note:

Only the pins that are 5V tolerant have an entry in the 5VT column in the Pin Description Table.

TABLE 2-2:

NUMBERED NOTES

NOTE

Description

Note 1

An external cap must be connected as close to the VR_CAP pin/ball as possible with a routing resistance

and CAP ESR of less than 100mohms. The capacitor value is 1uF and must be ceramic with X5R or X7R

dielectric. The cap pin/ball should remain on the top layer of the PCB and traced to the CAP. Avoid adding

vias to other layers to minimize inductance.

Note 2

This SMBus ports supports 1 Mbps operation as defined by I2C. For 1 Mbps I2C recommended capaci-

tance/pull-up relationships from Intel, refer to the Shark Bay platform guide, Intel ref number 486714. Refer

to the PCH - SMBus 2.0/SMLink Interface Design Guidelines, Bus Capacitance/Pull-Up Resistor Relation-

ship.

Note 4

The voltage on the ADC pins must not exceed 3.6 V or damage to the device will occur.

Note 5

The VCI pins may be used as GPIOs. The VCI input signals are not gated by selecting the GPIO alternate

function. Firmware must disable (i.e., gate) these inputs by writing the bits in the VCI Input Enable Register

when the GPIO function is enabled.

Note 6

The Over voltage protected GPIO pins will not support the Repeater mode mentioned in the GPIO pin con-

figuration register

Note 7

Refer Configurable Signal Routing section under Pin Configuration chapter for details on using the <signal>

and <signal>_ALT. Both <signal> and <signal>_ALT cannot be enabled simultaneously.

Note 8

<Signal> with ‘#’ as suffix will be shown as <Signal>_n in MPLab Tools

Note 9

32kHz_IN is named CLK32kHz_IN in MPLab Tools

Note 10 Clock Enable Register Bits [3:2] should be configured to be driven by single ended 32Khz source. Connect

the pin to SUSCLK from PCH.

Note 11 When the JTAG_RST# pin is not asserted (logic'1'), the JTAG or ARM SWJ signal functions in the JTAG

interface are unconditionally routed to the GPIO interface; the Pin Control register for these GPIO pins has

no effect.When the JTAG_RST# pin is asserted (logic'0'), the signal functions in the JTAG interface are not

routed to the interface and the Pin Control Register for these GPIO pins controls the muxing. The pin con-

trol registers can not route the JTAG interface to the pins. System Board Designer should terminate this pin

in all functional state using jumpers and pull-up or pull down resistors, etc.

Note 12 The JTAG signals TDI,TDO,TMS,TCK are muxed with GPIO pins. Routing of JTAG signals to these pins

are dependent on DEBUG ENABLE REGISTER bits [2:0] and JTAG_RST# pin (Note . To configure these

GPIO pins for non JTAG functions, pull JTAG_RST# low externally and select the appropriate alternate

function in the Pin Control Register

Note 13 The BGPO pins may be used as GPIO. For this the BGPO power control register and GPIO pin control reg-

ister needs to be configured

Note 14 GPIO000/VCI_IN3#, if not used must be connected to VBAT through a high impedance resistor of the order

of 100k

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