MMPF0100 datasheet(32/136 Pages) NXP

32 / 136 page

NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.3

Power tree

The PF0100 PMIC features six buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a DDR

voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost

regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they

are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators

depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied

by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR.

VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 28 for a summary of all power supplies provided by the

PF0100.

Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0100, as well as the

typical application voltage domain on the i.MX 6X processor. Note that each application power tree is dependent upon the system’s voltage

and current requirements, therefore a proper input voltage should be selected for the regulators.

The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial

power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative

tables and text specifying each supply for information on performance metrics and operating ranges. Table 29 summarizes the UVDET

thresholds.

Table 28. Power tree summary

Supply

Output voltage (V)

Step size (mV)

Maximum load current (mA)

SW1A/B

0.3 - 1.875

2500

SW1C

0.3 - 1.875

2000

SW2

0.4 - 3.3

25/50

2000 (43)

SW3A/B

0.4 - 3.3

25/50

1250 (42)

SW4

0.5*SW3A_OUT, 0.4 - 3.3

25/50

1000

SWBST

5.00/5.05/5.10/5.15

600

VGEN1

0.80 – 1.55

100

VGEN2

0.80 – 1.55

250

VGEN3

1.8 – 3.3

100

VGEN4

1.8 – 3.3

100

350

VGEN5

1.8 – 3.3

100

VGEN6

1.8 – 3.3

100

200

VSNVS

1.0 - 3.0

0.4

VREFDDR

0.5*SW3A_OUT

Notes

42.

Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up

to 2500 mA.

43.

SW2 capable of 2500 mA in NP, F9, and FA Industrial versions only (ANES suffix)

Table 29. UVDET threshold

UVDET threshold

VIN

Rising

3.1 V

Falling

2.65 V

MMPF0100 Datasheet(PDF) 32 Page - NXP Semiconductors

MMPF0100 Datasheet(HTML) 32 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL