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MMPF0100 Datasheet(PDF) 41 Page - NXP Semiconductors

Part # MMPF0100
Description  14 channel configurable power management integrated circuit
PDF  136 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0100 Datasheet(HTML) 41 Page - NXP Semiconductors

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NXP Semiconductors
41
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 13. SW1A/B dual phase, SW1C independent mode block diagram
In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 ° phase shift from each other and use the same
frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the
SW1CCONF register.
6.4.4.3.4
SW1A/B/C setup and control registers
SW1A/B and SW1C output voltages are programmable from 0.300 V to 1.875 V in steps of 25 mV. The output voltage set point is
independently programmed for normal, standby, and sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits
respectively. Table 41 shows the output voltage coding for SW1A/B or SW1C.
Note: Voltage set points of 0.6 V and below are not supported.
VIN
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW1AIN
SW1ALX
SW1FB
ISENSE
COSW1A
CINSW1A
LSW1A
I2C
Interface
SW1AB
SW1AMODE
SW1AFAULT
VREF
DAC
I2C
Driver
Controller
SW1BIN
SW1BLX
ISENSE
COSW1B
CINSW1B
LSW1B
SW1BMODE
SW1BFAULT
VIN
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW1CIN
SW1CLX
SW1CFB
ISENSE
COSW1C
CINSW1C
LSW1C
EP
SW1C
SW1CMODE
SW1CFAULT
VREF
DAC
I2C
VIN



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