MMPF0100 datasheet(82/136 Pages) NXP

82 / 136 page

NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as

programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 94

presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output.

For more detail information, Table 95 through Table 100 provide a description of all registers necessary to operate all six general purpose

LDO regulators.

0011

2.10

0100

2.20

0101

2.30

0110

2.40

0111

2.50

1000

2.60

1001

2.70

1010

2.80

1011

2.90

1100

3.00

1101

3.10

1110

3.20

1111

3.30

Table 94. LDO control

VGENxEN

VGENxLPWR

VGENxSTBY

STANDBY(64)

VGENxOUT

Off

Low power

Off

Low power

Notes

64.

STANDBY refers to a standby event as described earlier.

Table 95. Register VGEN1CTL - ADDR 0x6C

Name

Bit #

R/W

Default

Description

VGEN1

3:0

R/W

0x80

Sets VGEN1 output voltage.

See Table 92 for all possible configurations.

VGEN1EN

–

0x00

Enables or disables VGEN1 output

• 0 = OFF

• 1 = ON

VGEN1STBY

R/W

0x00

Set VGEN1 output state when in standby. Refer

to Table 94.

VGEN1LPWR

R/W

0x00

Enable low-power mode for VGEN1. Refer to

Table 94.

UNUSED

–

0x00

unused

Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration (continued)

Set point

VGENx[3:0]

VGENx output (V)

MMPF0100 Datasheet(PDF) 82 Page - NXP Semiconductors

MMPF0100 Datasheet(HTML) 82 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL