MMPF0100 datasheet(9/136 Pages) NXP

9 / 136 page

NXP Semiconductors

PF0100

PIN CONNECTIONS

VHALF

3.6 V

Analog

Half supply reference for VREFDDR

VINREFDDR

3.6 V

Analog

VREFDDR regulator input. Bypass with at least 1.0

μF decoupling capacitor

as close to the pin as possible.

VREFDDR

3.6 V

Analog

VREFDDR regulator output

SW3VSSSNS

GND

Ground reference for the SW3 regulator. Connect to GNDREF externally via

the board ground plane.

SW3BFB (6)

3.6 V

Analog

Output voltage feedback for SW3B. Route this trace separately from the high

current path and terminate at the output capacitance.

SW3BIN (6)

4.8 V

Analog

Input to SW3B regulator. Bypass with at least a 4.7

μF ceramic capacitor

and a 0.1

μF decoupling capacitor as close to the pin as possible.

SW3BLX (6)

4.8 V

Analog

Regulator 3B switch node connection

SW3ALX (6)

4.8 V

Analog

Regulator 3A switch node connection

SW3AIN (6)

4.8 V

Analog

Input to SW3A regulator. Bypass with at least a 4.7

μF ceramic capacitor

and a 0.1

μF decoupling capacitor as close to the pin as possible.

SW3AFB (6)

3.6 V

Analog

Output voltage feedback for SW3A. Route this trace separately from the high

current path and terminate at the output capacitance.

VGEN5

3.6 V

Analog

VGEN5 regulator output. Bypass with a 2.2

μF ceramic output capacitor.

VIN3

4.8 V

Analog

VGEN5, 6 input. Bypass with a 1.0

μF decoupling capacitor as close to the

pin as possible.

VGEN6

3.6 V

Analog

VGEN6 regulator output. By pass with a 2.2

μF ceramic output capacitor.

LICELL

I/O

3.6 V

Analog

Coin cell supply input/output

VSNVS

3.6 V

Analog

LDO or coin cell output to processor

SWBSTFB (6)

5.5 V

Analog

Boost regulator feedback. Connect this pin to the output rail close to the

load. Keep this trace away from other noisy traces and planes.

SWBSTIN (6)

4.8 V

Analog

Input to SWBST regulator. Bypass with at least a 2.2

μF ceramic capacitor

and a 0.1

μF decoupling capacitor as close to the pin as possible.

SWBSTLX (6)

7.5 V

Analog

SWBST switch node connection

VDDOTP

10 V(5)

Digital and

Analog

Supply to program OTP fuses

GNDREF

GND

Ground reference for the main band gap regulator.

VCORE

3.6 V

Analog

Analog Core supply

VIN

4.8 V

Analog

Main chip supply

VCOREDIG

1.5 V

Analog

Digital Core supply

VCOREREF

1.5 V

Analog

Main band gap reference

SDA

I/O

3.6 V

Digital

I2C data line (Open drain)

SCL

3.6 V

Digital

I2C clock

VDDIO

3.6 V

Analog

Supply for I2C bus. Bypass with 0.1

μF ceramic capacitor

PWRON

3.6 V

Digital

Power On/off from processor

GND

Expose pad. Functions as ground return for buck regulators. Tie this pad to

the inner and external ground planes through vias to allow effective thermal

dissipation.

Notes

10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.

Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be

connected to VIN with a 0.1

μF bypass capacitor.

Table 4. PF0100 pin definitions (continued)

Pin number

Pin name

function

Max rating

Type

Definition

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