MCIMX503CVM8B datasheet(14/136 Pages) NXP

14 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Modules List

Freescale Semiconductor

GPU2Dv1

Graphics

Processing

Unit-2D, ver. 1

Display

Peripherals

The GPU2Dv1 provides hardware acceleration for 2D graphic algorithms with

sufficient processor power to run desk-top quality interactive graphics

applications on displays up to HD1080 resolution.

I2C-1

I2C-2

I2C-3

I2C Interface

Connectivity

Peripherals

I2C provides serial interface for controlling peripheral devices. Data rates of

up to 400 kbps are supported.

OCOTP

Controller

On-chip OTP

controller

Security

Peripherals

The on-chip one-time -programmable (OCOTP) ROM serves the functions of

hardware and software capability bits, Freescale operations and unique-ID,

the customer-programmable cryptography key, and storage of various ROM

and general purpose configuration bits.

IOMUXC

IOMUX Control Slave

Connectivity

Peripherals

This module enables flexible I/O multiplexing. Each I/O pad has default as

well as several alternate functions. The alternate functions are software

configurable.

KPP

Keypad Port

Slave

Connectivity

Peripherals

The KPP supports an 8

× 8 external keypad matrix. The KPP features are as

follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

OWIRE

One-Wire

Interface

Slave

Connectivity

Peripherals

One-Wire support provided for interfacing with an on-board EEPROM, and

smart battery interfaces, for example, Dallas DS2502.

PWM-1

PWM-2

Pulse Width

Modulation

Slave

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images. It can also generate tones.

The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.

RAM

128 Kbytes

Internal RAM

Internal

Memory

The On-Chip Memory controller (OCRAM) module, is an interface between

the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is

used for controlling the 128 Kbyte multimedia RAM, through a 64-bit AXI bus.

ROM

96 Kbytes

Boot ROM

Internal

Memory

Supports secure and regular Boot Modes.

The ROM Controller supports ROM Patching.

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

MCIMX503CVM8B Datasheet(PDF) 14 Page - NXP Semiconductors

MCIMX503CVM8B Datasheet(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL