MCIMX503CVM8B datasheet(49/136 Pages) NXP

49 / 136 page

Electrical Characteristics

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

NOTE

CKIL is approximately 32 kHz. TCKIL is one period or approximately

μs.

4.6.3

Clock Amplifier Parameters (CKIH)

The input to clock amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave

or sinusoidal frequency source. No external series capacitors are required.

Table 38 shows the electrical parameters of CAMP.

4.6.4

DPLL Electrical Parameters

Table 39 shows the electrical parameters of digital phase-locked loop (DPLL).

Table 37. WDOG_RST_B Timing Parameters

Parameter

Min

Max

Unit

CC5

Duration of WDOG_RST_B Assertion

—

TCKIL

Table 38. CAMP Electrical Parameters (CKIH)

Parameter

Min

Typ

Max

Unit

Input frequency

8.0

—

40.0

MHz

VIL (for square wave input)

—

0.3

VIH (for square wave input)

(VCC1 – 0.25)

1 VCC is the supply voltage of CAMP.

—3

Sinusoidal input amplitude

0.4 2

2 This value of the sinusoidal input is determined during characterization.

—

VDD

Vp-p

Output duty cycle

Table 39. DPLL Electrical Parameters

Parameter

Test Conditions/Remarks

Min

Typ

Max

Unit

Reference clock frequency range1

—10

—

100

MHz

Reference clock frequency range after

pre-divider

—10

—

MHz

Output clock frequency range (dpdck_2)

—

300

—

1025

MHz

Pre-division factor2

—1

—

Multiplication factor integer part

—

Multiplication factor numerator3

Should be less than denominator

–67108862

—

67108862

—

Multiplication factor denominator2

—

67108863

—

Output duty cycle

—

48.5

51.5

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