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MCIMX503CVM8B Datasheet(PDF) 34 Page - NXP Semiconductors |
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MCIMX503CVM8B Datasheet(HTML) 34 Page - NXP Semiconductors |
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34 / 136 page  i.MX50 Applications Processors for Consumer Products, Rev. 7 Electrical Characteristics Freescale Semiconductor 34 4.3.3 Low Power DDR2 I/O DC Parameters The LPDDR2 interface fully complies with JEDEC standard release April, 2008. The parameters in Table 20 are guaranteed per the operating ranges in Table 11, unless otherwise noted. 4.3.4 Low Power DDR1 I/O DC Parameters The LPDDR1 interface fully complies with JEDEC standard release April, 2008. The parameters in Table 21 are guaranteed per the operating ranges in Table 11, unless otherwise noted. Table 20. LPDDR2 I/O DC Electrical Parameters DC Electrical Characteristics Symbol Test Conditions MIN TYP MAX Units High-level output voltage Voh — 0.9*ovdd — — V Low-level output voltage Vol — — — 0.1*ovdd V Input reference voltage Vref — 0.49*ovdd 0.5*ovdd 0.51*ovdd — DC input high voltage Vih(dc) — Vref+0.13 — ovdd V DC input low voltage Vil(dc) — ovss — Vref-0.13 V Differential input logic high1 1 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Vih(diff) — 0.26 — — V Differential input logic low1 Vil(diff) — — — -0.26 V Input current (no pull-up/down) Iin VI = 0 VI=ovdd —0.02 1.5 12.8 290 nA Tri-state I/O supply current2 2 Typ condition: typ model, 1.2V, and 25 °C. Max condition: BCS model, 1.3V, and 125 °C. Min condition: WCS model, 1.14V, and -40 °C. Icc-ovdd VI = ovdd or 0 — 1.85 400 nA Tri-state 2.5 V predrivers supply current2 Icc-vdd2p5 VI = ovdd or 0 — 5 700 nA Tri-state core supply current2 Icc-vddi VI = ovdd or 0 — 3 700 nA Pullup/Pulldown impedance mismatch2 —— -15 — +15 % 240 Ω unit calibration resolution — — — — 10 Ω Table 21. LPDDR1 Mode DC Electrical Characteristics DC Electrical Characteristics Symbol Test Conditions MIN TYP MAX Units High-level output voltage Voh Ioh=-0.1mA 0.9*ovdd — — V Low-level output voltage Vol Iol=0.1mA — — 0.1*ovdd V DC input high voltage (data pins) Vihd(dc) — 0.7*ovdd — ovdd+0.3 V DC input low voltage (data pins) Vild(dc) — -0.3 — 0.3*ovdd V DC input voltage1 (clk pins) Vin(dc) — -0.3 — ovdd+0.3 V DC input differential voltage2 Vid(dc) — 0.4*ovdd — ovdd+0.6 V Input current3 (no pull-up/down) Iin VI = 0 VI=ovdd —0.07 2 5 360 nA Tri-state I/O supply current3 Icc-ovdd VI = ovdd or 0 — 2.3 480 nA Tri-state 2.5V predrivers supply current3 Icc-vdd2 p5 VI = ovdd or 0 — 5.3 680 nA Tri-state core supply current3 Icc-vddi VI = ovdd or 0 — 3.1 720 nA |
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