MCIMX503CVM8B datasheet(48/136 Pages) NXP

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i.MX50 Applications Processors for Consumer Products, Rev. 7

Electrical Characteristics

Freescale Semiconductor

4.6

System Modules Timing

This section contains the timing and electrical parameters for the modules in the i.MX50 processor.

4.6.1

Reset Timings Parameters

Figure 6 shows the reset timing and Table 36 lists the timing parameters.

Figure 6. Reset Timing Diagram

4.6.2

WDOG Reset Timing Parameters

Figure 7 shows the WDOG reset timing and Table 37 lists the timing parameters.

Figure 7. WDOG_RST_B Timing Diagram

Single output slew rate

(Driver impedance =40

Ω+/-30%)

tsr

1.5

3.5

V/ns

Single output slew rate

(Driver impedance =60

Ω+/-30%

tsr

2.5

V/ns

1Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the

“true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to

Vih(ac)-Vil(ac).

2The typical value of Vix(ac) is expected to be about 0.5*OVDD. and Vix(ac) is expected to track

variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

Table 36. Reset Timing Parameters

Parameter

Min

Max

Unit

CC1

Duration of RESET_IN_B assertion to be qualified as valid (input slope =

5ns)

—

Table 35. LPDDR2 I/O AC Parameters (continued)

Parameter

Symbol

Min

Max

Unit

RESET_IN_B

CC1

(Input)

WDOG_RST_B

CC5

(Input)

MCIMX503CVM8B Datasheet(PDF) 48 Page - NXP Semiconductors

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