MCIMX503CVM8B datasheet(84/136 Pages) NXP

84 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Electrical Characteristics

Freescale Semiconductor

Figure 43 depicts Write 0 Sequence timing, and Table 61 lists the timing parameters.

Figure 43. Write 0 Sequence Timing Diagram

Figure 44 depicts Write 1 Sequence timing, Figure 45 depicts the Read Sequence timing, and Table 62

lists the timing parameters.

Figure 44. Write 1 Sequence Timing Diagram

Table 60. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Symbol

Min

Typ

Max

Unit

OW1

Reset Time Low

tRSTL

480

511

—1

1 In order not to mask signaling by other devices on the 1-Wire bus, t

RSTL +tR should always be less than 960 µs.

µs

OW2

Presence Detect High

tPDH

—

µs

OW3

Presence Detect Low

tPDL

—

240

µs

OW4

Reset Time High

(includes recovery time)

tRSTH

480

512

—

µs

Table 61. WR0 Sequence Timing Parameters

Parameter

Symbol

Min

Typ

Max

Unit

OW5

Write 0 Low Time

tLOW0

100

120

µs

OW6

Transmission Time Slot

tSLOT

OW5

117

120

µs

—

Recovery time

tREC

1—

—

µs

OW5

OW6

One-Wire bus

(BATT_LINE)

tREC

OW7

OW8

One-Wire bus

(BATT_LINE)

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