MCIMX503CVM8B datasheet(6/136 Pages) NXP

6 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Introduction

Freescale Semiconductor

•USB:

— One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY

— One High Speed (HS) USB 2.0 host port with integrated HS USB PHY

•

Miscellaneous interfaces:

— One-wire (OWIRE) port

— Two I2S/SSI/AC97 ports, supporting up to 1.4 Mbps each connected to the Audio Multiplexer

(AUDMUX) providing four external ports

— Five UART RS232 ports, up to 4.0 Mbps each

— Two eCSPI (Enhanced CSPI) ports, up to 66 Mbps each plus CSPI port, up to 16.6 Mbps

—Three I2C ports, supporting 400 kbps

— Fast Ethernet controller IEEE 802.3, 10/100 Mbps

— Key pad port (KPP)

— Two pulse width modulators (PWM)

— GPIO with interrupt capabilities

— Secure JTAG controller (SJC)

The system supports efficient and smart power control and clocking:

•

Supporting DVFS techniques for low power modes, including auto slow architecture

•

Power gating-SRPG (state retention power gating) for ARM core and NEON

•

Support for various levels of system power modes

•

Flexible clock gating control scheme

•

On-chip temperature monitor

•

On-chip 32 kHz and 24 MHz oscillators

•

A total of four PLLs with the fourth PLL providing up to eight independently controllable outputs,

improving the ease of clocking control, especially for display and connectivity modules

Security functions are enabled and accelerated by the following hardware:

•

Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or

blocking the access to the system debug features

•

Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and

mechanism to detect voltage and clock glitches

•

Advanced high assurance boot (A-HAB)—HAB with the next embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

MCIMX503CVM8B Datasheet(PDF) 6 Page - NXP Semiconductors

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