MCIMX503CVM8B datasheet(80/136 Pages) NXP

80 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Electrical Characteristics

Freescale Semiconductor

4.9.4

FEC AC Timing Parameters

This section describes the AC timing specifications of the FEC. The i.MX50 FEC supports 10/100 Mbps

RMII with MII serial management interface. The RMII and serial management signals are compatible with

transceivers operating at a voltage of 3.3 V.

4.9.4.1

RMII Async Inputs Signal Timing (FEC_COL)

Table 56 lists RMII asynchronous inputs signal timing information. Figure 38 shows MII asynchronous

input timings listed in Table 56.

Figure 38. MII Async Inputs Timing Diagram

4.9.4.2

RMII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 57 lists RMII serial management channel timings. Figure 39 shows RMII serial management

channel timings listed in Table 57. The MDC frequency should be equal to or less than 2.5 MHz to be

compliant with the IEEE 802.3 RMII specification. However, the FEC can function correctly with a

maximum MDC frequency of 15 MHz.

SD2

eSDHC Output Delay

tOD

–5

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD3

eSDHC Input Setup Time

tISU

2.5

—

SD4

eSDHC Input Hold Time

tIH

1.5

—

Table 56. RMII Async Inputs Signal Timing

Num

Characteristics

Min

Max

Unit

FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

Table 57. RMII Transmit Signal Timing

Characteristics

Min

Max

Unit

M10

FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

—

M11

FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

—

M12

FEC_MDIO (input) to FEC_MDC rising edge setup

—

M13

FEC_MDIO (input) to FEC_MDC rising edge hold

—

Table 55. eMMC4.4 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

FEC_COL

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