MCIMX503CVM8B datasheet(68/136 Pages) NXP

68 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Electrical Characteristics

Freescale Semiconductor

4.8

DRAM Timing Parameters

This section includes descriptions of the electrical specifications of DRAM MC module which interfaces

external DDR2, LPDDR1, and LPDDR2 memory devices.

WE34

EIM_RW invalid to EIM_CSx invalid

WE7 – WE9 + (WEN – CSN)

—

3 – (WEN_CSN)

WE35

EIM_CSx valid to EIM_OE valid

WE10 – WE6 + (OEA – CSA)

—

3 + (OEA – CSA)

WE36

EIM_OE invalid to EIM_CSx invalid

WE7 – WE11 + (OEN – CSN)

—

3 – (OEN – CSN)

WE37

EIM_CSx valid to EIM_EBx valid

(Read access)

WE12 – WE6 + (RBEA – CSA)

—

3 + (RBEA4 – CSA)

WE38

EIM_EBx invalid to EIM_CSx invalid

(Read access)

WE7 – WE13 + (RBEN – CSN)

—

3 – (RBEN5 – CSN)

WE39

EIM_CSx valid to EIM_LBA valid

WE14 – WE6 + (ADV – CSA)

—

3 + (ADVA – CSA)

WE40

EIM_LBA invalid to EIM_CSx invalid

(ADVL is asserted)

WE7 – WE15 – CSN

—

3 – CSN

WE41

EIM_CSx valid to Output Data valid

WE16 – WE6 – WCSA

—

3 – WCSA

WE42

Output Data invalid to EIM_CSx

invalid

WE17 – WE7 – CSN

—

3 – CSN

WE43

Input Data valid to EIM_CSx invalid

MAXCO + MAXDI

MAXCO6 +

MAXDI7

—ns

WE44

EIM_CSx invalid to Input Data invalid

—

WE45

EIM_CSx valid to EIM_EBx valid

(Write access)

WE12 – WE6 + (WBEA – CSA)

—

3 + (WBEA – CSA)

WE46

EIM_EBx invalid to EIM_CSx invalid

(Write access)

WE7 – WE13 + (WBEN – CSN)

—

–3 + (WBEN – CSN)

WE47

EIM_DTACK valid to EIM_CSx

invalid

MAXCO + MAXDTI

MAXCO6 +MA

XDTI8

—ns

WE48

EIM_CSx invalid to EIM_DTACK

invalid

—

1 Parameters WE4–WE21 value, see in the Table 44.

2 EIM_CSx Assertion. This bit field determines when EIM_CSx signal is asserted during read/write cycles.

3 EIM_CSx Negation. This bit field determines when EIM_CSx signal is negated during read/write cycles.

4 EIM_EBx Assertion. This bit field determines when EIM_EBx signal is asserted during read cycles.

5 EIM_EBx Negation. This bit field determines when EIM_EBx signal is negated during read cycles.

6 Output maximum delay from internal driving the FFs to chip outputs. The maximum delay between all memory controls

(EIM_ADDR, EIM_CSx, EIM_OE, EIM_RW, EIM_EBx, and EIM_LBA).

7 Maximum delay from chip input data to internal FFs. The maximum delay between all data input pins.

8 DTACK maximum delay from chip input data to internal FF.

Table 44. EIM Asynchronous Timing Parameters Table Relative Chip Select (continued)

Parameter

Determination by

Synchronous Measured

Parameters 1

Min

Max

Unit

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