AD4697BCPZ datasheet(47/107 Pages) AD

47 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 47 of 107

Streaming Mode

When the INST_MODE bit in the SPI_CONFIG_B register is set

to 0, streaming mode is enabled. In streaming mode, only one in-

struction phase is required per SPI frame, and the register address

being read from or written to is automatically updated after each

data phase (based on the selected address direction option). The

instruction phase is followed by multiple data phases for each

mode enables efficient access to large, contiguous sections of the

configuration register map, such as when updating the advanced

sequencer slot registers (AS_SLOTn) to configure the advanced

sequencer.

Figure 84 shows a generalized SPI frame for performing multiple

Because there is only one instruction phase per frame in streaming

mode, all SPI transactions in a given SPI frame are either all reads

or all writes. The checksum is included in each data phase only if

CRC is enabled (see the Checksum Protection section).

Figure 85 to Figure 87 show examples of accessing different parts

of the register map with both address direction options and with

both MB_STRICT options (see the Multibyte Register Access sec-

tion).

When streaming mode is active, a specified number of registers

can be looped to repeatedly access the same registers multiple

times in a single SPI frame. The LOOP_COUNT bit field in

the LOOP_MODE register determines how many registers are ac-

cessed before the register address is reset to the starting address

(the one specified in the instruction phase). When the MB_STRICT

bit is set to 1, a multibyte register is considered one register when

looping. When the MB_STRICT bit is set to 0, each byte of a

multibyte register is considered one register when looping.

Figure 88 shows an example using looping to repeatedly read from

the ALERT_STATUS1 and ALERT_STATUS2 registers.

If the LOOP_COUNT bit field is set to 0x0, looping is disabled.

If looping is disabled and the descending address option is se-

lected, the address decrements until it reaches Address 0x0000,

and the address is set to the highest valued register address

available (Address 0x013F) on the subsequent byte access. If

looping is disabled and the ascending address option is selected,

the address increments until it reaches the highest valued register

address available (Address 0x013F), and the address is set to Ad-

dress 0x0000 on the subsequent byte access. Looping is disabled

by default.

Note that even when using 7-bit addressing, registers with address-

es larger than 0xFF are still accessible in streaming mode. Howev-

er, accessing these registers is generally more efficient using 15-bit

addressing.

Single Instruction Mode

When the INST_MODE bit in the SPI_CONFIG_B register is set to

1, single instruction mode is enabled. In single instruction mode,

each SPI read or write transaction includes an instruction phase

to specify whether the transaction is a read or a write and what

address is being accessed. Single instruction mode allows the digi-

tal host to quickly read from or write to registers with nonadjacent

mode, which allows exclusively reading from or writing to registers

with adjacent addresses without starting a new SPI frame.

Figure 89 shows a generalized SPI frame for performing multiple

selected. The checksum is included in each data phase only if CRC

is enabled (see the Checksum Protection section).

Figure 90 shows an example of reading from and writing to the

most significant byte and least significant byte of the UPPER_IN1

ples of reading from the UPPER_IN1 register and writing to the

UPPER_IN0 register in the same frame with both address direction

options (MB_STRICT = 1). Note that the UPPER_INn registers are

multibyte registers, and when MB_STRICT is set to 1, both bytes

must be read from or written to in one data phase (see the Multibyte

Figure 84. Streaming Mode SPI Frame

AD4697BCPZ Datasheet(PDF) 47 Page - Analog Devices

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