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AD4697BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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AD4697BCPZ Datasheet(HTML) 10 Page - Analog Devices |
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10 / 107 page  Data Sheet AD4697/AD4698 SPECIFICATIONS analog.com Rev. 0 | 10 of 107 Table 2. Parameter1 Symbol Min Typ Max Unit AC_CYC = 0x5 170 200 230 μs AC_CYC = 0x6 340 400 460 μs AC_CYC = 0x7 680 800 920 μs CNV High Time tCNVH 10 ns CNV Low Time tCNVL 80 ns CS High Time tCSBH 5 ns CS Low to Digital Interface Ready Delay tEN 15 ns CS High to SDO High Impedance Delay tCSBDIS 15 ns SCK Period tSCK Register Configuration Mode 40 ns Conversion Mode 12.5 ns SCK Low Time tSCKL Register Configuration Mode 16 ns Conversion Mode 5 ns SCK High Time tSCKH Register Configuration Mode 16 ns Conversion Mode 5 ns SDI Data Setup Time Prior to SCK Rising Edge tSSDI 2 ns SDI Data Hold Time After SCK Rising Edge tHSDI 2 ns SCK Falling Edge to Data Remains Valid Delay tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO 10.5 ns Last SCK Edge to CNV Rising Edge Delay tSCKCNV 80 ns Last SCK Rising Edge to CS Rising Edge Delay tSCKCSB 1 ns CNV Rising Edge to Busy Indicator Rising Edge (Busy Indicator Enabled on General-Purpose Pin) tCNVBSY 20 ns CNV Rising Edge to Alert Indicator Transition (Alert Indicator Enabled on General-Purpose Pin) tCNVALT 425 ns Busy Indicator Low Time, Autocycle Mode Enabled (Busy Indicator Enabled on General-Purpose Pin) tACBSY AC_CYC = 0x0 8 µs AC_CYC = 0x1 16.5 µs AC_CYC = 0x2 33.5 µs AC_CYC = 0x3 67.5 µs AC_CYC = 0x4 84.5 µs AC_CYC = 0x5 169 µs AC_CYC = 0x6 339 µs AC_CYC = 0x7 679 µs Register Configuration Mode Setup Time tREGCONFIG 20 ns RESET Low Time tRESETL 10 ns Hardware Reset Delay (VDD Always Supplied) tHWR_DELAY 310 µs Software Reset Delay tSWR_DELAY 310 µs VDD Power-On Reset Delay tPOR_VDD 2 ms VIO Power-On Reset Delay (VDD Supplied Externally) tPOR_VIO1 1.3 ms LDO_IN Power-On Reset Delay tPOR_LDO 3.2 ms VIO Power-On Reset Delay (VDD Supplied by Internal LDO) tPOR_VIO2 3 ms LDO Wake-Up Command Power-On Reset Delay tWAKEUP_SW 3 ms Hardware Reset Delay (Internal LDO Disabled) tWAKEUP_HW 3 ms 1 For all specifications, the relative voltages for the AVDD and REF inputs follow the operating conditions specified in the reference and power requirements sections of Table 1. 2 The acquisition time for single-cycle command mode depends on the sample rate and SCK frequency (see the Single-Cycle Command Mode section). |
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