AD4697BCPZ datasheet(56/107 Pages) AD

56 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 56 of 107

Conversion Mode Timing Diagrams

Figure 94 to Figure 101 show detailed timing diagrams for perform-

ing analog-to-digital conversions when the AD4697/AD4698 are in

conversion mode with each serial data output mode option (with

autocycle mode disabled).

When the device is in conversion mode, a CNV rising edge initiates

a conversion and enters the conversion phase (see the Converter

Operation section). When a conversion is initiated, it continues until

completion regardless of the state of CNV. When the standard

sequencer, advanced sequencer, or two-cycle command mode is

enabled, the device enters the acquisition phase before the con-

version phase is complete. When single-cycle command mode is

enabled, the device enters the acquisition phase after the sixth SCK

rising edge in the SPI frame. Figure 94 to Figure 99 and Figure 101

show tACQ when the standard sequencer, advanced sequencer, or

two-cycle command mode is enabled. Figure 100 shows tACQ when

single-cycle command mode is enabled.

CS frames the conversion result data. While CS is high, SCK edges

are ignored, and all pins assigned as serial data outputs are high

impedance. While CS is low, data is clocked out with the MSB first

on one or more serial data outputs on the SCK falling edges, and

data is latched in on the SDI on the SCK rising edges.

CNV and CS can be tied together and driven by the chip select

of the host SPI to minimize the number of digital signals required

to interface with the AD4697/AD4698 (see the SPI Peripheral

Connections section). Figure 101 shows a timing diagram of the

AD4697/AD4698 interfacing with a 4-wire SPI with the CNV and CS

signals tied together.

The conversion phase must be complete before the digital host

provides the first SCK falling edge. The digital host can use the

busy indicator falling edge to detect the end of the conversion

phase and to begin clocking out the ADC results. Otherwise, the

digital host must include a delay dictated by the conversion time

specification (tCONVERT) in Table 2 between the CNV rising edge

and the first SCK falling edge.

The 5-bit SDI commands shown in Table 18 are latched in on the

SDI on the first five SCK rising edges in the SPI frame. The register

configuration mode command instructs the AD4697/AD4698 to exit

conversion mode and enter register configuration mode (see the

lect commands in Table 18 are only used when two-cycle command

mode or single-cycle command mode is enabled. These commands

are interpreted as NOOP commands when the standard sequencer

or the advanced sequencer is enabled (see the Channel Sequenc-

ing Modes section).

To ensure optimal performance, there must be a sufficient delay

between the final SCK edge and the next CNV rising edge, and

there must be no SCK activity until the conversion time has elapsed

(see tSCKCNV in Table 2 and Figure 94 to Figure 101).

The SDO_STATE bit in the setup register determines the behavior

of the serial data output(s) at the beginning and the end of the

conversion mode SPI frames. When the SDO_STATE bit is set to

0, the serial data output(s) hold their final value(s) until the MSB of

the next conversion result is clocked out. The serial data output(s)

remain in this state even if multiple extra SCK falling edges occur

after the full result is shifted out. The serial data output(s) are forced

to high impedance when CS is brought high, but return to the

previous state after CS is brought low again. Figure 94, Figure 96

and Figure 98 show the behavior of the serial data output(s) when

SDO_STATE is set to 0. SDO_STATE is set to 0 by default.

When SDO_STATE is set to 1, the busy indicator is enabled on

the serial data output(s) (see the Busy Indicator section). The serial

data output(s) are forced to high impedance if any SCK falling

edges occur after the final bits of the result are already clocked

out, or when CNV or CS is brought high. When a CNV rising

edge initiates a conversion, the serial data output(s) remain high

impedance until the conversion phase is complete, and the result

is available to be read over the SPI. The serial data output(s) are

driven low when the data is ready. If the current selected channel

has an OSR greater than 1, the serial data output(s) are driven low

after the oversampled result is ready. Note that CS must be driven

low for the busy indicator to appear on the serial data output(s).

When the busy indicator is enabled on a general-purpose pin,

the selected general-purpose pin is driven high after a CNV rising

edge and is driven low when the conversion is complete (see the

Busy Indicator on General-Purpose Pins section). The BUSY signal

in Figure 94 to Figure 100 represents the general-purpose pin as-

signed as the busy indicator. Figure 78 in the Channel Sequencing

Modes section shows the relative timing of the CNV rising edge and

the busy indicator for OSR settings of 1 and greater than 1.

When the threshold detection alert indicator is enabled on a gener-

al-purpose pin, the selected general-purpose pin reflects the value

of the TD_ALERT bit in the status register. The ALERT signal in

Figure 94 to Figure 99 represents the general-purpose pin assigned

as the alert indicator. Figure 78 in the Channel Sequencing Modes

section show the relative timing of the CNV rising edge and the

alert indicator for OSR settings of 1 and greater than 1.

The register configuration mode command is a 5-bit command

written on the SDI that instructs the device to exit conversion mode

and enter register configuration mode. The register configuration

mode command is 0x0A. Figure 102 shows the relative timing of

the register configuration mode command and the AD4697/AD4698

entering register configuration mode.

The register configuration mode command is clocked in on the SDI

on the first five SCK rising edges after a conversion. When the

rising edge on CS places the AD4697/AD4698 in register configu-

ration mode. The digital host must wait for the tREGCONFIG delay

AD4697BCPZ Datasheet(PDF) 56 Page - Analog Devices

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