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AD4697BCPZ Datasheet(PDF) 70 Page - Analog Devices

Part # AD4697BCPZ
Description  16-Bit, 8-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC
PDF  107 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4697BCPZ Datasheet(HTML) 70 Page - Analog Devices

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Data Sheet
AD4697/AD4698
APPLICATIONS INFORMATION
analog.com
Rev. 0 | 70 of 107
ANALOG FRONT-END DESIGN
The AFE companion circuitry for the AD4697/AD4698 normally
includes an external RC filter and an ADC driver or a precision
operational amplifier between the signal being measured and the
AD4697/AD4698 analog inputs.
The component selection and design of the AFE circuitry driving the
AD4697/AD4698 analog inputs have a direct impact on the overall
system performance. The AFE must be designed with the system
target noise, accuracy, distortion, and settling requirements of the
end application. The following sections provide recommendations
for designing AFE and signal conditioning circuits based on these
requirements.
External RC Filter
The external RC low-pass filter consists of an external resistor and
capacitor (represented by REXT and CEXT in Figure 66 and
Figure 112). These components act to reduce the wideband noise
from the AFE circuitry, reduce the nonlinear voltage kickback that
occurs at the analog inputs, and protect the analog inputs from
overvoltage events. Selecting the appropriate REXT and CEXT val-
ues for these functions is described in the Analog Front-End Noise
Considerations section, the Signal Settling Requirements section,
and the Analog Input Overvoltage Protection section.
Ensure that the CEXT capacitor is an NP0 ceramic capacitor to limit
distortion artifacts, and that the PCB layout minimizes the parasitic
impedance between CEXT and the analog input pin. See the Layout
Guidelines section for more information.
Signal Settling Requirements
As described in the Converter Operation and Analog Inputs sec-
tions, the AD4697/AD4698 analog inputs (IN0 to IN7 and COM) are
routed to the ADC core inputs via the internal analog multiplexer.
As shown in Figure 66, the ADC core capacitive DAC can be
represented by a switched capacitive load.
At the start of the conversion phase, the multiplexer switches are
disconnected and the voltage on the currently selected analog input
channel is sampled on the capacitive DAC. During the acquisition
phase, the multiplexer switches (SWMUX+ and SWMUX−) close to
connect the next selected analog input channel to the capacitive
DAC. A voltage glitch (commonly referred to as kickback) occurs
when these switches close due to the difference between the
voltage on the capacitive DAC and the voltage on the selected
analog input pins.
To achieve the specified performance of the AD4697/AD4698, this
kickback must be settled to within half an LSB of the ADC core
before the start of the next conversion phase (that is, the next
CNV rising edge). The rate at which the kickback voltage is settled
depends on the transient characteristics and bandwidth of the AFE
circuitry. Signal settling requirements therefore dictate the minimum
allowable AFE bandwidth and constrain the driver amplifier and
external RC filter selection.
Table 26 provides a list of recommended amplifiers and external RC
filter components for various sample rates and signal bandwidths.
Figure 71 and Figure 72 in the Analog Input High-Z Mode section
show SNR and THD performance with various amplifiers and exter-
nal RC component values.
Analog input high-Z mode significantly reduces the bandwidth re-
quirements of the AFE by minimizing the size of the voltage kick-
back. Figure 21 shows the difference in magnitude of the kickback
when analog input high-Z mode is disabled and enabled.
Analog Front-End Noise Considerations
The magnitude of the AFE noise directly impacts the dynamic range
and SNR performance of the overall AD4697/AD4698 signal chain.
Select the AFE components and configuration to achieve the target
noise specification for the overall system.
Figure 113 illustrates the primary noise sources in a typical analog
front-end driver circuit.
Figure 113. Noise Sources in Typical ADC AFE Circuit



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