AD4697BCPZ datasheet(77/107 Pages) AD

77 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

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Rev. 0 | 77 of 107

features require additional digital resources, such as GPIOs and

timers.

The following sections provide recommendations for digital in-

terface connections and operation to interact with the AD4697/

AD4698 interface and feature set.

ADC Convert Start Signal Options

The CNV input is analogous to an edge triggered interrupt pin,

which instructs the AD4697/AD4698 ADC core to perform a con-

version (see the Converter Operation section). The CNV input is

active only when the AD4697/AD4698 are in conversion mode and

is ignored when in register configuration mode. The period of the

signal driving the CNV input sets the sample rate of the AD4697/

AD4698 and must conform to the tCYC specification in Table 2 and

in Figure 94 through Figure 101.

The ADC core samples the analog input voltage on the selected

channel on the rising edge of CNV. The signal driving the CNV input

therefore must have sufficiently low jitter and fast edge rates to ach-

ieve the desired noise performance at the target input frequencies.

The layout of the trace connecting the AD4697/AD4698 CNV input

to the digital host must be as short as possible with minimal vias to

minimize trace impedance (see the Layout Guidelines section).

In conversion mode, the digital host SPI peripheral must be syn-

chronous to the CNV signal and follow the timing requirements

specified in the Conversion Mode Timing Diagrams section. See

the SPI Peripheral Synchronization in Conversion Mode section for

recommendations for maintaining proper SPI timing.

Embedded clock divider or timer peripherals can typically output

an integer division of the system clock. When utilizing embedded

clock divider peripherals, connect the digital host clock output to

CNV and set the clock output frequency to the desired sample rate.

The clock output must be enabled while the AD4697/AD4698 are in

conversion mode, but it can be either enabled or disabled while in

The CNV input can be connected to the CS output of the host SPI

peripheral, provided that the CS rising edge timing is deterministic

and periodic (see Figure 121). Note that for OSR settings greater

than 1, multiple CNV rising edges are required before the result

is available to be read out on the SPI (see the Oversampling and

Decimation section). The SPI outputs all 0s during the CNV/CS

frames prior to the oversampled data being ready.

An external crystal oscillator with a CMOS clock driver can also

drive the CNV input. With this option, either the oscillator output

or the busy indicator from the AD4697/AD4698 must be routed

to the digital host and used as a timer or interrupt trigger to

achieve synchronization between the CNV signal and the host SPI

peripheral (see the SPI Peripheral Synchronization in Conversion

Mode section).

Note that when autocycle mode is enabled, the CNV input is ignor-

ed, and conversions are instead triggered by an internal timer in

the AD4697/AD4698, as described in the Autocycle Mode section.

When exclusively using autocycle mode, the CNV input must be

tied to IOGND. The busy indicator is required to synchronize the

AD4697/AD4698 to the host SPI peripheral when using autocycle

mode (see the SPI Peripheral Synchronization in Autocycle Mode

section).

SPI Peripheral Connections

The AD4697/AD4698 offer multiple serial data output modes that

allow for one, two, or four main in, subordinate out (MISO) lines

to output conversion results (see the Serial Data Output Modes

section). When single-SDO mode is selected, only the SDO pin

functions as a serial data output. When dual-SDO mode or quad-

SDO mode is selected, the general-purpose pins are assigned as

additional serial data outputs to implement multiple data lanes.

Figure 118. AD4697/AD4698 SPI Connection Diagram (Single-SDO Mode)

Figure 118 shows a connection diagram for interfacing the AD4697/

AD4698 SPI to the digital host SPI peripheral when configured in

single-SDO mode. It is recommended to include a pull-up resistor

(2 kΩ minimum) to VIO on the SDO line, especially when the busy

indicator is enabled on SDO (see the Busy Indicator on Serial Data

Outputs section).

Figure 119. AD4697/AD4698 SPI Connection Diagram (Dual-SDO Mode)

Figure 119 shows a connection diagram for interfacing the AD4697/

AD4698 SPI to a digital host SPI peripheral when configured in

dual-SDO mode. Route BSY_ALT_GP0 to the second MISO input

on the digital host (MISO1). It is recommended to include pull-up

resistors on both SDO0 and SDO1 lines, especially when the

busy indicator is enabled on the serial data outputs (see the Busy

Indicator on Serial Data Outputs section).

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