AD4697BCPZ datasheet(78/107 Pages) AD

78 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

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Rev. 0 | 78 of 107

Figure 120. AD4698 SPI Connection Diagram (Quad-SDO Mode)

Figure 120 shows a connection diagram for interfacing the AD4698

SPI to a digital host SPI peripheral when configured in quad-SDO

mode (available on the WLCSP option only). Table 19 shows

the general-purpose pin assignments on the LFCSP and WCLSP

options for dual-SDO mode and quad-SDO mode. Route the pins

assigned as SDO1, SDO2, and SDO3 the additional MISO inputs

on the digital host (MISO1, MISO2, and MISO3, respectively).

It is recommended to include pull-up resistors on all pins assigned

as serial data outputs as shown in Table 19, especially when

the busy indicator is enabled on SDO (see the Busy Indicator on

Serial Data Outputs section). It is also recommended to include

pull-up resistors on the CS, SCK, and SDI lines if the outputs on

the host SPI peripheral are expected to be tristate or undefined

during operation. The specific value of the pull-up resistors must

be determined based on the edge rate requirements and trace

capacitance for each line.

SPI Peripheral Synchronization in Conversion

Mode

The AD4697/AD4698 have a 4-wire SPI in SPI Mode 3 for access-

ing register contents and ADC results. The digital host must at

minimum include a 4-wire SPI-compatible peripheral to operate the

AD4697/AD4698 (see the SPI Peripheral Connections section).

In conversion mode, the SPI transfers must begin after tCONVERT

has elapsed and must complete within tSCKCNV before the next

CNV rising edge (see Table 2 and in the timing diagrams in the

Conversion Mode Timing Diagrams section). To ensure that the

conversion mode timing requirements are met, the digital host

SPI peripheral must either be synchronized to the clock source

generating the CNV signal or to the busy indicator output from the

AD4697/AD4698. The SCK frequency must also be sufficiently high

to ensure that all conversion mode results are clocked out before

the start of the next conversion frame (see the Conversion Mode

SPI Clock Frequency Requirements section).

Figure 121 shows a simplified connection diagram and software

architecture for operating the AD4697/AD4698 with only a 4-wire

SPI. The CNV input is driven by the CS output from the digital

host SPI peripheral. The configuration in Figure 121 requires the

CS signal to be periodic with deterministic rising edge timing to

achieve the necessary jitter for the application. Synchronize the SPI

frames to a timer peripheral, and the CS output must have a well

defined duty cycle. Figure 101 shows a SPI timing diagram using

the configuration in Figure 121.

Figure 122 shows a simplified connection diagram and software

architecture for using the digital host countdown timer peripheral to

synchronize the host SPI peripheral to the CNV signal source. The

countdown timer is configured to trigger on a CNV rising edge, wait

for tCONVERT to elapse, and then trigger an interrupt service routine

that calls the SPI peripheral to perform a transfer. The countdown

timer is programmed with an integer value (count), which specifies

the number of system clock (SYS_CLK) periods to wait before

calling the SPI transfer interrupt routine. It is recommended to

implement a delay corresponding to the maximum tCONVERT specifi-

cation given in Table 2. In practice, most digital hosts exhibit some

latency between the interrupt service routine triggers and execution,

which increases the delay between the CNV rising edge and the

start of the SPI transfer. Refer to the digital host specifications to

determine the optimal count value for the given application.

Figure 123 shows a simplified connection diagram and software

architecture for utilizing the AD4697/AD4698 busy indicator to syn-

chronize the host SPI peripheral to the ADC conversion timing.

The busy indicator must be enabled on the BSY_ALT_GP0 or GP3

pin as described in the Busy Indicator on General-Purpose Pins

section, and the digital host must have a digital input that can be

configured as a trigger for interrupt service routines. Route the busy

indicator to the interrupt input on the digital host and configure the

interrupts to trigger on the busy indicator falling edge. Because the

busy indicator falling edge is interpreted as the data ready signal,

the digital host is not required to implement any further delays

between the busy indicator falling edge and the start of the SPI

frame.

The configuration in Figure 123 is recommended when utilizing

oversampling because the busy indicator does not go low until the

oversampled result is ready, reducing the number of redundant SPI

transfers that otherwise occur without additional logic (see

Figure 78).

Figure 124 shows a simplified connection diagram and software

architecture for utilizing the AD4697/AD4698 threshold detection

alert indicator to synchronize the host SPI peripheral to the ADC

conversion timing. The alert indicator must be enabled on the

BSY_ALT_GP0 or GP2 pin as described in the Alert Indicator on

General-Purpose Pins section. The configuration in Figure 124 is

ideal in autonomous conversion applications, where the SPI is idle

while the ADC continuously converts until a user defined, out of

bounds condition occurs. The alert indicator is updated at the end

of the conversion phase of the ADC and can therefore be used

as the trigger to start the SPI frame if the SPI frame can be

completed before the start of the next conversion. Typically, the

interrupt service routine called by the alert indicator rising edge

calls the SPI to read back the conversion result and sends the

AD4697/AD4698 into register configuration mode.

AD4697BCPZ Datasheet(PDF) 78 Page - Analog Devices

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