AD4697BCPZ datasheet(98/107 Pages) AD

98 / 107 page

Data Sheet

AD4697/AD4698

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Rev. 0 | 98 of 107

Table 45. Bit Descriptions for Setup

Bits

Bit Name

Description

Reset

Access

STATUS_EN

Status Bits Enable Bit. This bit determines whether the status bits are appended to conversion data when in

conversion mode (see the Status Bits section).

0x0

R/W

0: status bits disabled.

1: status bits enabled.

LDO_EN

Internal LDO Enable Bit. This bit enables or disables the internal LDO. Disable the internal LDO when driving VDD

with an external 1.8 V supply. When the internal LDO is supplying VDD, disabling the internal LDO removes power to

VDD and disables the ADC core and configuration registers (see the Internal LDO section).

0x1

R/W

0: internal LDO disabled.

1: internal LDO enabled.

RESERVED

Reserved.

0x0

R/W

SPI_MODE

Digital Interface Mode Select Bit. This bit determines whether the device is in register configuration mode or

conversion mode. Set this bit to 1 to enter conversion mode. This bit is set to 0 when the register configuration mode

command is received (see the Register Configuration Mode Command section).

0x0

R/W

0: selects register configuration mode.

1: selects conversion mode.

CYC_CTRL

Two- and Single-Cycle Command Mode Control Bit. This bit selects between two-cycle command mode and

single-cycle command mode. This bit must be set to 0 when using two-cycle command mode, the standard sequencer,

or the advanced sequencer (see the Channel Sequencing Modes section).

0x0

R/W

0: selects two-cycle command mode.

1: selects single-cycle command mode.

RESERVED

Reserved.

0x0

R/W

Reference Control Register

Address: 0x0021, Reset: 0x12, Name: REF_CTRL

Table 46. Bit Descriptions for REF_CTRL

Bits

Bit Name

Description

Reset

Access

OV_MODE

Overvoltage Reduced Current Mode Enable Bit. This bit enables or disables overvoltage reduced current mode

(see the Input Overvoltage Protection Clamps section).

0x0

R/W

0: reduces the REF current during clamping.

1: do not reduce REF current during clamping.

REFBUF_BP

Reference Buffer Bypass Control. Determines whether the reference buffer is bypassed (see the Internal Reference

Buffer section). If the REFBUF_EN bit is set to 1, the reference buffer is not bypassed, and this bit is ignored. This

bit is only active on the WLCSP option. Setting this bit on the LFCSP option has no effect.

0x0

R/W

0: internal reference buffer not bypassed.

1: internal reference buffer bypassed.

REFBUF_BOOST

Reference Buffer Boost Mode Enable Bit. Enables or disables reference buffer boost mode (see the Internal

Reference Buffer section). This bit is only active on the WLCSP option. Setting this bit on the LFCSP option has no

effect.

0x0

R/W

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