AM6421 datasheet(9/260 Pages) TI

9 / 260 page

• (GPMC and NOR Flash — Synchronous Mode): Changed the "not_div_by_1_mode"minimum value in the

"Hold time, input wait GPMC_WAIT[j] valid after output clock GPMC_CLK high (th(clkH-waitV))" parameter from

2.9 to 2.29 to correct a typographical error.....................................................................................................147

• (GPMC and NAND Flash — Asynchronous Mode): Removing the TBD maximum value from the "Pulse

duration, output write enable GPMC_WEn valid (tw(wenV))" parameter since a maximum value is not

applicable for this parameter.......................................................................................................................... 165

• (I2C Timing): Removed all timing parameter tables and diagrams, and referenced the Philips I2C-bus™

specification version 2.1 as the source for this information. Added per port descriptions that define each

speed mode supported and included additional information that details exceptions to the I2C specification 171

• (I2C Timing): Added per port descriptions that define each speed mode supported and included additional

information that details exceptions to the I2C specification............................................................................ 171

• (MCSPI - Controller Mode): Inclusive Nomenclature Updates....................................................................... 174

• (MCSPI - Peripheral Mode): Inclusive Nomenclature Updates.......................................................................176

• (OSPI Switching Characteristics – PHY Data Training): Defined values for all previously undefined TBD

values............................................................................................................................................................. 196

• (OSPI0 Timing Requirements – PHY SDR Mode): Updated all setup and hold values..................................198

• (PRU_ICSSM UART Timing Conditions): Changed the minimum and maximum values for Input Slew Rate,

and added a note to the maximum output load capacitance value in the Timing Conditions table................ 215

• (PRU_ICSSG UART Timing Requirements): Changed the description for each pulse width parameter, added

a note that clarifies the data valid time requirements for each parameter in the Timing Requirements table 215

• (PRU_ICSSG UART Timing Requirements and Switching Characteristics): Updated the timing diagram to

show RXD timing relative to VIL and VIH ........................................................................................................215

• (UART Timing Conditions): Added a note to the maximum output load capacitance value in the Timing

Conditions table.............................................................................................................................................. 225

• (UART Timing Requirements): Changed the start pulse width parameter description and added a note that

clarifies the data valid time requirements for each parameter in the Timing Requirements table.................. 225

• (UART Switching Characteristics): Added a new row for Programmable baud rate with different limits for Main

Domain and MCU Domain UARTs..................................................................................................................225

• (UART Switching Characteristics): Changed the start pulse width parameter description, removed the CTS

delay parameter, and removed the load capacitance references from the Programmable baud rate parameter

........................................................................................................................................................................225

• (UART Timing Requirements and Switching Characteristics): Updated the timing diagram to remove CTS and

show RXD timing relative to VIL and VIH ........................................................................................................225

• (UART): Updated maximum baud rate from 3.6864 Mbps to 12 Mbps on all UARTs except MCU_UART0 and

MCU_UART1..................................................................................................................................................238

• (Universal Serial Bus Subsystem): Removed references to OTG support and USB SuperSpeed support when

operating as USB device................................................................................................................................ 239

• (Power Supply Designs): Changed section title from "Power Supply Decoupling and Bulk Capacitors" to

"Power Supply"............................................................................................................................................... 240

• (Power Supply Designs): Changed section title from "Power Supply Mapping" to "Power Supply Designs" and

included PMIC recommendations and associated content links.....................................................................240

• Updating the xref href attribute value to correct ti.com link. (ZF)no................................................................240

• (Device Naming Convention): Changed descriptions associated with Feature codes to clarify PRU_ICSSG

features are still enabled on devices that do not enable Industrial Communication Support, and changed the

Security feature code from "Other" to "H".......................................................................................................250

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AM6442, AM6441, AM6422, AM6421, AM6412, AM6411

SPRSP56E – JANUARY 2021 – REVISED SEPTEMBER 2022

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