STM32U5A5QJ datasheet(48/382 Pages) STMICROELECTRONICS

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Functional overview

STM32U5Axxx

48/382

DS13543 Rev 1

3.9.4

Reset mode

In order to improve the consumption under reset, the I/O state under and after reset is

“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.9.5

VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or

an external super-capacitor.

The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers

and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.

The VBAT operation is automatically activated when VDD is not present. An internal

VBAT battery charging circuit is embedded and can be activated when VDD is present.

Note:

When the microcontroller is supplied from VBAT, neither external interrupts nor RTC

alarm/events exit the microcontroller from the VBAT operation.

3.9.6

PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in

TrustZone security mode.

The PWR TrustZone security secures the following configuration:

•

low-power mode

•

WKUP (wake-up) pins

•

voltage detection and monitoring

•

VBAT mode

6. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.

7. Sub-blocks or full SRAM1, SRAM3, and SRAM5, full SRAM2 and SRAM4 can be powered-off to save power consumption.

SRAM1, SRAM2, SRAM3, SRAM4, and SRAM5 can be accessed by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be

accessed by LPDMA1 in Stop 0, Stop 1 and Stop 2 modes.

8. GPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.

9. LPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.

10. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16, MSIS or MSIK to be

enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.

11. OTG_HS is functional in voltage scaling range 1 and 2.

12. USART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and in SPI

master modes, and generate a wake-up interrupt on transfer events.

13. I2C reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt on transfer

events.

14. SPI reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt on transfer

events.

15. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on conversion events.

16. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.

17. MDF and ADF are functional and autonomous in Stop mode, and generate a wake-up interrupt on events.

18. I/Os can be configured with internal pull-up, pull-down or floating in Stop 3 and Standby modes.

19. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

STM32U5A5QJ Datasheet(PDF) 48 Page - STMicroelectronics

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