STM32U5A5QJ datasheet(65/382 Pages) STMICROELECTRONICS

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DS13543 Rev 1

65/382

STM32U5Axxx

Functional overview

The HSPI registers can be configured as secure through the TZSC controller.

3.31

Analog-to-digital converters (ADC1, ADC2 and ADC4)

The devices embed three successive approximation analog-to-digital converters.

3.31.1

Analog-to-digital converters (ADC1/2)

The ADC1/2 are 14-bit ADC successive approximation analog-to-digital converters.

Each ADC has up to 20 multiplexed channels. A/D conversion of the various channels can

be performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is

stored in a left-aligned or right-aligned 32-bit data register.

The ADC1/2 are mapped on the AHB bus to allow fast data handling. The analog watchdog

features allow the application to detect if the input voltage goes outside the user-defined

high or low thresholds.

A built-in hardware over sampler allows analog performances to be improved while

off-loading the related computational burden from the CPU.

An efficient low-power mode is implemented to allow very low consumption at low

frequency.

Table 15. ADC features

ADC modes/features(1)

1. X = supported.

ADC1

ADC2

ADC4

Resolution

14 bits

12 bits

Maximum sampling speed for 14-bit resolution

2.5 Msps

Hardware offset calibration

Hardware linearity calibration

Single-ended inputs

Differential inputs

Injected channel conversion

Oversampling

up to x1024

up to x256

Data register

32 bits

16 bits

DMA support

Parallel data output to MDF

Dual mode

Autonomous mode

Offset compensation

Gain compensation

Number of analog watchdogs

Wake-up from Stop mode

X(2)

2. wake-up supported from Stop 0, Stop 1 and Stop 2 modes.

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