STM32U5A5QJ datasheet(76/382 Pages) STMICROELECTRONICS

76 / 382 page

Functional overview

STM32U5Axxx

76/382

DS13543 Rev 1

The LTDC main features are:

•

24-bit RGB parallel pixel output; 8 bits-per-pixel (RGB888)

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2 display layers with dedicated FIFO (64x32-bit)

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Color look-up table (CLUT) up to 256 color (256x24-bit) per layer

•

Programmable timings for different display panels

•

Programmable background color

•

Programmable polarity for HSYNC, VSYNC and data enable

•

Up to 8 input color formats selectable per layer:

–

ARGB8888

–

RGB888

–

RGB565

–

ARGB1555

–

ARGB4444

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L8 (8-bit luminance or CLUT)

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AL44 (4-bit alpha + 4-bit luminance)

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AL88 (8-bit alpha + 8-bit luminance)

•

Pseudo-random dithering output for low bits per channel

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Dither width 2 bits for Red, Green, Blue

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Flexible blending between two layers using alpha value (per pixel or constant)

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Color keying (transparency color)

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Programmable window position and size

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Supports thin film transistor (TFT) color displays

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AHB master interface with burst of 16 words

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Up to 4 programmable interrupt events

3.40

DSI Host controller (DSI)

The display serial interface (DSI) is part of a group of communication protocols defined by

the MIPI Alliance. The MIPI DSI Host controller is a digital core that implements all protocol

functions defined in the MIPI DSI specification. It provides an interface between the system

(LTDC and APB interface) and the MIPI D-PHY, allowing the user to communicate with a

DSI-compliant display.

The DSI main features are:

•

Compliant with MIPI Alliance standards

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Interface with internal MIPI D-PHY

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Supports all commands defined in the MIPI Alliance specification for DCS:

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Transmission of all command mode packets through the APB interface

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Transmission of commands in low-power and high-speed during video mode

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Support of up to 2 D-PHY data lanes

•

Bidirectional communication and escape mode support through data lane 0

•

Support of non-continuous clock in D-PHY clock lane for additional power saving

•

Support of ultra low-power mode with PLL disabled

•

ECC and checksum capabilities

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